X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fmips_m4k.c;h=fe99773d873f866267fb4f2ff3ee98e481394a9f;hp=b1a4e46abeaed652c42dc7b049a14b1cf005202e;hb=f876d5e9c769a288faa7fd14b7bf373363542aab;hpb=6fda8707668c413a78f44ae4f58a79f5765376c2 diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c index b1a4e46abe..fe99773d87 100644 --- a/src/target/mips_m4k.c +++ b/src/target/mips_m4k.c @@ -26,11 +26,8 @@ #include "mips32.h" #include "mips_m4k.h" #include "mips32_dmaacc.h" -#include "jtag.h" -#include "log.h" +#include "target_type.h" -#include -#include /* cli handling */ @@ -40,8 +37,8 @@ int mips_m4k_halt(struct target_s *target); int mips_m4k_soft_reset_halt(struct target_s *target); int mips_m4k_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution); int mips_m4k_step(struct target_s *target, int current, u32 address, int handle_breakpoints); -int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); -int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); +int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer); +int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer); int mips_m4k_register_commands(struct command_context_s *cmd_ctx); int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target); int mips_m4k_quit(void); @@ -93,7 +90,7 @@ target_type_t mips_m4k_target = int mips_m4k_examine_debug_reason(target_t *target) { - int break_status; + u32 break_status; int retval; if ((target->debug_reason != DBG_REASON_DBGRQ) @@ -164,7 +161,7 @@ int mips_m4k_poll(target_t *target) u32 ejtag_ctrl = ejtag_info->ejtag_ctrl; /* read ejtag control reg */ - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); @@ -174,7 +171,7 @@ int mips_m4k_poll(target_t *target) { /* we have detected a reset, clear flag * otherwise ejtag will not work */ - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC; mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); @@ -187,7 +184,7 @@ int mips_m4k_poll(target_t *target) { if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) { - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL); target->state = TARGET_HALTED; @@ -238,7 +235,7 @@ int mips_m4k_halt(struct target_s *target) if (target->state == TARGET_RESET) { - if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst) + if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) { LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST"); return ERROR_TARGET_FAILURE; @@ -270,6 +267,7 @@ int mips_m4k_assert_reset(target_t *target) LOG_DEBUG("target->state: %s", Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); + enum reset_types jtag_reset_config = jtag_get_reset_config(); if (!(jtag_reset_config & RESET_HAS_SRST)) { LOG_ERROR("Can't assert SRST"); @@ -279,12 +277,12 @@ int mips_m4k_assert_reset(target_t *target) if (target->reset_halt) { /* use hardware to catch reset */ - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL); } else { - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL); } @@ -348,8 +346,11 @@ int mips_m4k_single_step_core(target_t *target) /* configure single step mode */ mips_ejtag_config_step(ejtag_info, 1); + /* disable interrupts while stepping */ + mips32_enable_interrupts(target, 0); + /* exit debug mode */ - mips_ejtag_exit_debug(ejtag_info, 1); + mips_ejtag_exit_debug(ejtag_info); mips_m4k_debug_entry(target); @@ -401,8 +402,11 @@ int mips_m4k_resume(struct target_s *target, int current, u32 address, int handl } } - /* exit debug mode - enable interrupts if required */ - mips_ejtag_exit_debug(ejtag_info, !debug_execution); + /* enable interrupts if we are running */ + mips32_enable_interrupts(target, !debug_execution); + + /* exit debug mode */ + mips_ejtag_exit_debug(ejtag_info); target->debug_reason = DBG_REASON_NOTHALTED; /* registers are now invalid */ @@ -456,8 +460,11 @@ int mips_m4k_step(struct target_s *target, int current, u32 address, int handle_ target_call_event_callbacks(target, TARGET_EVENT_RESUMED); + /* disable interrupts while stepping */ + mips32_enable_interrupts(target, 0); + /* exit debug mode */ - mips_ejtag_exit_debug(ejtag_info, 1); + mips_ejtag_exit_debug(ejtag_info); /* registers are now invalid */ mips32_invalidate_core_regs(target); @@ -524,7 +531,7 @@ int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { u32 verify = 0xffffffff; - if((retval = target->type->read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK) + if((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK) { return retval; } @@ -545,9 +552,9 @@ int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) } else { - u16 verify = 0xffff; + uint16_t verify = 0xffff; - if((retval = target->type->read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK) + if((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK) { return retval; } @@ -606,13 +613,13 @@ int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) u32 current_instr; /* check that user program has not modified breakpoint instruction */ - if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)¤t_instr)) != ERROR_OK) + if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (uint8_t*)¤t_instr)) != ERROR_OK) { return retval; } if (current_instr == MIPS32_SDBBP) { - if((retval = target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) + if((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) { return retval; } @@ -620,17 +627,17 @@ int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) } else { - u16 current_instr; + uint16_t current_instr; /* check that user program has not modified breakpoint instruction */ - if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)¤t_instr)) != ERROR_OK) + if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t*)¤t_instr)) != ERROR_OK) { return retval; } if (current_instr == MIPS16_SDBBP) { - if((retval = target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) + if((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) { return retval; } @@ -721,7 +728,7 @@ void mips_m4k_enable_watchpoints(struct target_s *target) } } -int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer) +int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer) { mips32_common_t *mips32 = target->arch_info; mips_ejtag_t *ejtag_info = &mips32->ejtag_info; @@ -741,26 +748,41 @@ int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 cou if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) return ERROR_TARGET_UNALIGNED_ACCESS; - switch (size) - { - case 4: - case 2: - case 1: - /* if noDMA off, use DMAACC mode for memory read */ - if(ejtag_info->impcode & EJTAG_IMP_NODMA) - return mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer); - else - return mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer); - default: - LOG_ERROR("BUG: we shouldn't get here"); - exit(-1); - break; + /* if noDMA off, use DMAACC mode for memory read */ + int retval; + if(ejtag_info->impcode & EJTAG_IMP_NODMA) + retval = mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer); + else + retval = mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer); + if (ERROR_OK != retval) + return retval; + + /* TAP data register is loaded LSB first (little endian) */ + if (target->endianness == TARGET_BIG_ENDIAN) + { + u32 i, t32; + uint16_t t16; + + for(i = 0; i < (count*size); i += size) + { + switch(size) + { + case 4: + t32 = le_to_h_u32(&buffer[i]); + h_u32_to_be(&buffer[i], t32); + break; + case 2: + t16 = le_to_h_u16(&buffer[i]); + h_u16_to_be(&buffer[i], t16); + break; + } + } } return ERROR_OK; } -int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer) +int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer) { mips32_common_t *mips32 = target->arch_info; mips_ejtag_t *ejtag_info = &mips32->ejtag_info; @@ -780,24 +802,33 @@ int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 co if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) return ERROR_TARGET_UNALIGNED_ACCESS; - switch (size) - { - case 4: - case 2: - case 1: - /* if noDMA off, use DMAACC mode for memory write */ - if(ejtag_info->impcode & EJTAG_IMP_NODMA) - mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer); - else - mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer); - break; - default: - LOG_ERROR("BUG: we shouldn't get here"); - exit(-1); - break; - } + /* TAP data register is loaded LSB first (little endian) */ + if (target->endianness == TARGET_BIG_ENDIAN) + { + u32 i, t32; + uint16_t t16; - return ERROR_OK; + for(i = 0; i < (count*size); i += size) + { + switch(size) + { + case 4: + t32 = be_to_h_u32(&buffer[i]); + h_u32_to_le(&buffer[i], t32); + break; + case 2: + t16 = be_to_h_u16(&buffer[i]); + h_u16_to_le(&buffer[i], t16); + break; + } + } + } + + /* if noDMA off, use DMAACC mode for memory write */ + if(ejtag_info->impcode & EJTAG_IMP_NODMA) + return mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer); + else + return mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer); } int mips_m4k_register_commands(struct command_context_s *cmd_ctx) @@ -849,9 +880,9 @@ int mips_m4k_examine(struct target_s *target) mips_ejtag_t *ejtag_info = &mips32->ejtag_info; u32 idcode = 0; - if (!target->type->examined) + if (!target_was_examined(target)) { - mips_ejtag_get_idcode(ejtag_info, &idcode, NULL); + mips_ejtag_get_idcode(ejtag_info, &idcode); ejtag_info->idcode = idcode; if (((idcode >> 1) & 0x7FF) == 0x29) @@ -873,7 +904,7 @@ int mips_m4k_examine(struct target_s *target) return ERROR_OK; } -int mips_m4k_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer) +int mips_m4k_bulk_write_memory(target_t *target, u32 address, u32 count, uint8_t *buffer) { return mips_m4k_write_memory(target, address, 4, count, buffer); }