X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Ftarget%2Fnslu2.cfg;fp=src%2Ftarget%2Ftarget%2Fnslu2.cfg;h=2ad71174346096bf4ca3d9419c1304288974e93e;hp=c545e01f3b23b631c299972581d6887160ac70b8;hb=a28eaa85f73759bb189a46308642502c9fa5aa4b;hpb=91afc3dc3083a3d4f6a4104a5132d87c8ec03c7f

diff --git a/src/target/target/nslu2.cfg b/src/target/target/nslu2.cfg
index c545e01f3b..2ad7117434 100644
--- a/src/target/target/nslu2.cfg
+++ b/src/target/target/nslu2.cfg
@@ -1,22 +1,8 @@
-# use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config srst_only
-
-# jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 7 0x1 0x7f 0x7e
-
-# target configuration
-target create target0 xscale -endian big -chain-position 0 -variant ixp42x
-
-
-# maps to PXA internal RAM.  If you are using a PXA255
-# you must initialize SDRAM or leave this option off
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00020000 -work-area-size 0x10000 -work-area-backup 0
-
-# flash bank <driver> <base> <size> <chip_width> <bus_width>
-#flash bank cfi 0x50000000 0x1000000 2 4 0 
-
-
+# This is for the LinkSys (CYSCO) LSLU2 board
+# It is an Intel XSCALE IPX420 CPU.
 
+source [find target/ipx42x.cfg]
+# The _TARGETNAME is set by the above.
 
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00020000 -work-area-size 0x10000 -work-area-backup 0