X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fx86_32_common.h;h=14e6e35f77b6f2401e11be77b95543e0d22da7be;hp=ef5a9ccae18b61a68a621ec397542264305603e1;hb=0627e4686aa18159327751361940595e19b0c525;hpb=1338cf60b91c582fa4b27d5226ab4374117be415
diff --git a/src/target/x86_32_common.h b/src/target/x86_32_common.h
index ef5a9ccae1..14e6e35f77 100644
--- a/src/target/x86_32_common.h
+++ b/src/target/x86_32_common.h
@@ -1,5 +1,5 @@
/*
- * Copyright(c) 2013 Intel Corporation.
+ * Copyright(c) 2013-2016 Intel Corporation.
*
* Adrian Burns (adrian.burns@intel.com)
* Thomas Faust (thomas.faust@intel.com)
@@ -8,8 +8,9 @@
* Jeffrey Maxwell (jeffrey.r.maxwell@intel.com)
*
* This program is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -17,8 +18,7 @@
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * along with this program. If not, see .
*
* Contact Information:
* Intel Corporation
@@ -29,11 +29,12 @@
* This is the interface to the x86 32 bit memory and breakpoint operations.
*/
-#ifndef X86_32_COMMON_H
-#define X86_32_COMMON_H
+#ifndef OPENOCD_TARGET_X86_32_COMMON_H
+#define OPENOCD_TARGET_X86_32_COMMON_H
#include
#include
+#include
extern const struct command_registration x86_32_command_handlers[];
@@ -42,27 +43,27 @@ extern const struct command_registration x86_32_command_handlers[];
#define WORD 2
#define DWORD 4
-#define EFLAGS_TF 0x00000100 /* Trap Flag */
-#define EFLAGS_IF 0x00000200 /* Interrupt Flag */
-#define EFLAGS_RF 0x00010000 /* Resume Flag */
-#define EFLAGS_VM86 0x00020000 /* Virtual 8086 Mode */
+#define EFLAGS_TF ((uint32_t)0x00000100) /* Trap Flag */
+#define EFLAGS_IF ((uint32_t)0x00000200) /* Interrupt Flag */
+#define EFLAGS_RF ((uint32_t)0x00010000) /* Resume Flag */
+#define EFLAGS_VM86 ((uint32_t)0x00020000) /* Virtual 8086 Mode */
-#define CSAR_DPL 0x00006000
-#define CSAR_D 0x00400000
-#define SSAR_DPL 0x00006000
+#define CSAR_DPL ((uint32_t)0x00006000)
+#define CSAR_D ((uint32_t)0x00400000)
+#define SSAR_DPL ((uint32_t)0x00006000)
-#define CR0_PE 0x00000001 /* Protected Mode Enable */
-#define CR0_NW 0x20000000 /* Non Write-Through */
-#define CR0_CD 0x40000000 /* Cache Disable */
-#define CR0_PG 0x80000000 /* Paging Enable */
+#define CR0_PE ((uint32_t)0x00000001) /* Protected Mode Enable */
+#define CR0_NW ((uint32_t)0x20000000) /* Non Write-Through */
+#define CR0_CD ((uint32_t)0x40000000) /* Cache Disable */
+#define CR0_PG ((uint32_t)0x80000000) /* Paging Enable */
/* TODO - move back to PM specific file */
-#define PM_DR6 0xFFFF0FF0
+#define PM_DR6 ((uint32_t)0xFFFF0FF0)
-#define DR6_BRKDETECT_0 0x00000001 /* B0 through B3 */
-#define DR6_BRKDETECT_1 0x00000002 /* breakpoint condition detected */
-#define DR6_BRKDETECT_2 0x00000004
-#define DR6_BRKDETECT_3 0x00000008
+#define DR6_BRKDETECT_0 ((uint32_t)0x00000001) /* B0 through B3 */
+#define DR6_BRKDETECT_1 ((uint32_t)0x00000002) /* breakpoint condition detected */
+#define DR6_BRKDETECT_2 ((uint32_t)0x00000004)
+#define DR6_BRKDETECT_3 ((uint32_t)0x00000008)
enum {
/* general purpose registers */
@@ -194,6 +195,11 @@ enum {
WBINVD,
};
+enum x86_core_type {
+ LMT1,
+ LMT3_5
+};
+
struct swbp_mem_patch {
uint8_t orig_byte;
uint32_t swbp_unique_id;
@@ -207,9 +213,11 @@ struct swbp_mem_patch {
struct x86_32_common {
uint32_t common_magic;
void *arch_info;
+ enum x86_core_type core_type;
struct reg_cache *cache;
struct jtag_tap *curr_tap;
uint32_t stored_pc;
+ int forced_halt_for_reset;
int flush;
/* pm_regs are for probemode save/restore state */
@@ -302,14 +310,14 @@ int x86_32_get_gdb_reg_list(struct target *t,
int x86_32_common_init_arch_info(struct target *target,
struct x86_32_common *x86_32);
int x86_32_common_mmu(struct target *t, int *enabled);
-int x86_32_common_virt2phys(struct target *t, uint32_t address, uint32_t *physical);
-int x86_32_common_read_phys_mem(struct target *t, uint32_t phys_address,
+int x86_32_common_virt2phys(struct target *t, target_addr_t address, target_addr_t *physical);
+int x86_32_common_read_phys_mem(struct target *t, target_addr_t phys_address,
uint32_t size, uint32_t count, uint8_t *buffer);
-int x86_32_common_write_phys_mem(struct target *t, uint32_t phys_address,
+int x86_32_common_write_phys_mem(struct target *t, target_addr_t phys_address,
uint32_t size, uint32_t count, const uint8_t *buffer);
-int x86_32_common_read_memory(struct target *t, uint32_t addr,
+int x86_32_common_read_memory(struct target *t, target_addr_t addr,
uint32_t size, uint32_t count, uint8_t *buf);
-int x86_32_common_write_memory(struct target *t, uint32_t addr,
+int x86_32_common_write_memory(struct target *t, target_addr_t addr,
uint32_t size, uint32_t count, const uint8_t *buf);
int x86_32_common_read_io(struct target *t, uint32_t addr,
uint32_t size, uint8_t *buf);
@@ -319,5 +327,6 @@ int x86_32_common_add_breakpoint(struct target *t, struct breakpoint *bp);
int x86_32_common_remove_breakpoint(struct target *t, struct breakpoint *bp);
int x86_32_common_add_watchpoint(struct target *t, struct watchpoint *wp);
int x86_32_common_remove_watchpoint(struct target *t, struct watchpoint *wp);
+void x86_32_common_reset_breakpoints_watchpoints(struct target *t);
-#endif /* X86_32_COMMON_H */
+#endif /* OPENOCD_TARGET_X86_32_COMMON_H */