X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fxscale.c;h=8f7d835152b6d8a73b7dca0c558e96b178446c6e;hp=cb673df686594793b920ba4b3fda22f55f499ef9;hb=4cb9b179059bb40badde110da5641dcbbd636a29;hpb=2e01a1ad1930aabb9e3bc7a0e3eb98b2b3331b1c diff --git a/src/target/xscale.c b/src/target/xscale.c index cb673df686..8f7d835152 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -53,8 +53,8 @@ int xscale_target_command(struct command_context_s *cmd_ctx, char *cmd, char **a int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *target); int xscale_quit(); -int xscale_arch_state(struct target_s *target, char *buf, int buf_size); -enum target_state xscale_poll(target_t *target); +int xscale_arch_state(struct target_s *target); +int xscale_poll(target_t *target); int xscale_halt(target_t *target); int xscale_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution); int xscale_step(struct target_s *target, int current, u32 address, int handle_breakpoints); @@ -84,6 +84,8 @@ int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint); int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint); void xscale_enable_watchpoints(struct target_s *target); void xscale_enable_breakpoints(struct target_s *target); +static int xscale_virt2phys(struct target_s *target, u32 virtual, u32 *physical); +static int xscale_mmu(struct target_s *target, int *enabled); int xscale_read_trace(target_t *target); @@ -122,7 +124,10 @@ target_type_t xscale_target = .register_commands = xscale_register_commands, .target_command = xscale_target_command, .init_target = xscale_init_target, - .quit = xscale_quit + .quit = xscale_quit, + + .virt2phys = xscale_virt2phys, + .mmu = xscale_mmu }; char* xscale_reg_list[] = @@ -189,11 +194,13 @@ int xscale_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, xsc if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { + ERROR("target isn't an XScale target"); return -1; } if (xscale->common_magic != XSCALE_COMMON_MAGIC) { + ERROR("target isn't an XScale target"); return -1; } @@ -218,8 +225,8 @@ int xscale_jtag_set_instr(int chain_pos, u32 new_instr) field.out_mask = NULL; field.in_value = NULL; jtag_set_check_value(&field, device->expected, device->expected_mask, NULL); - - jtag_add_ir_scan(1, &field, -1, NULL); + + jtag_add_ir_scan(1, &field, -1); free(field.out_value); } @@ -283,8 +290,6 @@ int xscale_read_dcsr(target_t *target) fields[1].in_handler_priv = NULL; fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; - - fields[2].device = xscale->jtag_info.chain_pos; fields[2].num_bits = 1; @@ -293,12 +298,12 @@ int xscale_read_dcsr(target_t *target) fields[2].in_value = NULL; jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL); - jtag_add_dr_scan(3, fields, -1, NULL); + jtag_add_dr_scan(3, fields, -1); if ((retval = jtag_execute_queue()) != ERROR_OK) { ERROR("JTAG error while reading DCSR"); - exit(-1); + return retval; } xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0; @@ -313,13 +318,19 @@ int xscale_read_dcsr(target_t *target) jtag_add_end_state(TAP_RTI); - jtag_add_dr_scan(3, fields, -1, NULL); + jtag_add_dr_scan(3, fields, -1); - return ERROR_OK; + /* DANGER!!! this must be here. It will make sure that the arguments + * to jtag_set_check_value() does not go out of scope! */ + return jtag_execute_queue(); } int xscale_receive(target_t *target, u32 *buffer, int num_words) { + if (num_words==0) + return ERROR_INVALID_ARGUMENTS; + + int retval=ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -336,7 +347,6 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) int words_scheduled = 0; int i; - int retval; path[0] = TAP_SDS; path[1] = TAP_CD; @@ -358,8 +368,8 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) fields[1].in_handler_priv = NULL; fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; - - + + fields[2].device = xscale->jtag_info.chain_pos; fields[2].num_bits = 1; @@ -373,6 +383,7 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) jtag_add_runtest(1, -1); /* repeat until all words have been collected */ + int attempts=0; while (words_done < num_words) { /* schedule reads */ @@ -384,14 +395,14 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) fields[1].in_handler_priv = (u8*)&field1[i]; jtag_add_pathmove(3, path); - jtag_add_dr_scan(3, fields, TAP_RTI, NULL); + jtag_add_dr_scan(3, fields, TAP_RTI); words_scheduled++; } if ((retval = jtag_execute_queue()) != ERROR_OK) { ERROR("JTAG error while receiving data from debug handler"); - exit(-1); + break; } /* examine results */ @@ -409,6 +420,16 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) words_scheduled--; } } + if (words_scheduled==0) + { + if (attempts++==1000) + { + ERROR("Failed to receiving data from debug handler after 1000 attempts"); + retval=ERROR_JTAG_QUEUE_FAILED; + break; + } + } + words_done += words_scheduled; } @@ -417,7 +438,7 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) free(field1); - return ERROR_OK; + return retval; } int xscale_read_tx(target_t *target, int consume) @@ -425,6 +446,7 @@ int xscale_read_tx(target_t *target, int consume) armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; enum tap_state path[3]; + enum tap_state noconsume_path[9]; int retval; struct timeval timeout, now; @@ -444,6 +466,16 @@ int xscale_read_tx(target_t *target, int consume) path[1] = TAP_CD; path[2] = TAP_SD; + noconsume_path[0] = TAP_SDS; + noconsume_path[1] = TAP_CD; + noconsume_path[2] = TAP_E1D; + noconsume_path[3] = TAP_PD; + noconsume_path[4] = TAP_E2D; + noconsume_path[5] = TAP_UD; + noconsume_path[6] = TAP_SDS; + noconsume_path[7] = TAP_CD; + noconsume_path[8] = TAP_SD; + fields[0].device = xscale->jtag_info.chain_pos; fields[0].num_bits = 3; fields[0].out_value = NULL; @@ -460,8 +492,8 @@ int xscale_read_tx(target_t *target, int consume) fields[1].in_handler_priv = NULL; fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; - - + + fields[2].device = xscale->jtag_info.chain_pos; fields[2].num_bits = 1; @@ -482,18 +514,18 @@ int xscale_read_tx(target_t *target, int consume) if (consume) jtag_add_pathmove(3, path); else - jtag_add_statemove(TAP_PD); + jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path); - jtag_add_dr_scan(3, fields, TAP_RTI, NULL); + jtag_add_dr_scan(3, fields, TAP_RTI); if ((retval = jtag_execute_queue()) != ERROR_OK) { ERROR("JTAG error while reading TX"); - exit(-1); + return ERROR_TARGET_TIMEOUT; } gettimeofday(&now, NULL); - if ((now.tv_sec > timeout.tv_sec) && (now.tv_usec > timeout.tv_usec)) + if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec))) { ERROR("time out reading TX register"); return ERROR_TARGET_TIMEOUT; @@ -543,8 +575,8 @@ int xscale_write_rx(target_t *target) fields[1].in_handler_priv = NULL; fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; - - + + fields[2].device = xscale->jtag_info.chain_pos; fields[2].num_bits = 1; @@ -557,19 +589,19 @@ int xscale_write_rx(target_t *target) timeval_add_time(&timeout, 5, 0); /* poll until rx_read is low */ + DEBUG("polling RX"); do { - DEBUG("polling RX"); - jtag_add_dr_scan(3, fields, TAP_RTI, NULL); + jtag_add_dr_scan(3, fields, TAP_RTI); if ((retval = jtag_execute_queue()) != ERROR_OK) { ERROR("JTAG error while writing RX"); - exit(-1); + return retval; } gettimeofday(&now, NULL); - if ((now.tv_sec > timeout.tv_sec) && (now.tv_usec > timeout.tv_usec)) + if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec))) { ERROR("time out writing RX register"); return ERROR_TARGET_TIMEOUT; @@ -578,12 +610,12 @@ int xscale_write_rx(target_t *target) /* set rx_valid */ field2 = 0x1; - jtag_add_dr_scan(3, fields, TAP_RTI, NULL); + jtag_add_dr_scan(3, fields, TAP_RTI); if ((retval = jtag_execute_queue()) != ERROR_OK) { ERROR("JTAG error while writing RX"); - exit(-1); + return retval; } return ERROR_OK; @@ -602,7 +634,6 @@ int xscale_send(target_t *target, u8 *buffer, int count, int size) scan_field_t fields[3]; u8 field0_out = 0x0; - u8 field0_in = 0x0; u8 field0_check_value = 0x2; u8 field0_check_mask = 0x6; u8 field2 = 0x1; @@ -617,8 +648,11 @@ int xscale_send(target_t *target, u8 *buffer, int count, int size) fields[0].num_bits = 3; fields[0].out_value = &field0_out; fields[0].out_mask = NULL; - fields[0].in_value = &field0_in; - jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL); + fields[0].in_handler = NULL; + if (!xscale->fast_memory_access) + { + jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL); + } fields[1].device = xscale->jtag_info.chain_pos; fields[1].num_bits = 32; @@ -629,45 +663,72 @@ int xscale_send(target_t *target, u8 *buffer, int count, int size) fields[1].in_handler_priv = NULL; fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; - - + + fields[2].device = xscale->jtag_info.chain_pos; fields[2].num_bits = 1; fields[2].out_value = &field2; fields[2].out_mask = NULL; fields[2].in_value = NULL; - jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL); - - while (done_count++ < count) + fields[2].in_handler = NULL; + if (!xscale->fast_memory_access) { - /* extract sized element from target-endian buffer, and put it - * into little-endian output buffer - */ - switch (size) + jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL); + } + + if (size==4) + { + int endianness = target->endianness; + while (done_count++ < count) { - case 4: - buf_set_u32(output, 0, 32, target_buffer_get_u32(target, buffer)); - break; - case 2: - buf_set_u32(output, 0, 32, target_buffer_get_u16(target, buffer)); - break; - case 1: - output[0] = *buffer; - break; - default: - ERROR("BUG: size neither 4, 2 nor 1"); - exit(-1); + if (endianness == TARGET_LITTLE_ENDIAN) + { + output[0]=buffer[0]; + output[1]=buffer[1]; + output[2]=buffer[2]; + output[3]=buffer[3]; + } else + { + output[0]=buffer[3]; + output[1]=buffer[2]; + output[2]=buffer[1]; + output[3]=buffer[0]; + } + jtag_add_dr_scan(3, fields, TAP_RTI); + buffer += size; } + + } else + { + while (done_count++ < count) + { + /* extract sized element from target-endian buffer, and put it + * into little-endian output buffer + */ + switch (size) + { + case 2: + buf_set_u32(output, 0, 32, target_buffer_get_u16(target, buffer)); + break; + case 1: + output[0] = *buffer; + break; + default: + ERROR("BUG: size neither 4, 2 nor 1"); + exit(-1); + } - jtag_add_dr_scan(3, fields, TAP_RTI, NULL); - buffer += size; + jtag_add_dr_scan(3, fields, TAP_RTI); + buffer += size; + } + } if ((retval = jtag_execute_queue()) != ERROR_OK) { ERROR("JTAG error while sending data to debug handler"); - exit(-1); + return retval; } return ERROR_OK; @@ -725,8 +786,8 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) fields[1].in_handler_priv = NULL; fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; - - + + fields[2].device = xscale->jtag_info.chain_pos; fields[2].num_bits = 1; @@ -735,12 +796,12 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) fields[2].in_value = NULL; jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL); - jtag_add_dr_scan(3, fields, -1, NULL); + jtag_add_dr_scan(3, fields, -1); if ((retval = jtag_execute_queue()) != ERROR_OK) { ERROR("JTAG error while writing DCSR"); - exit(-1); + return retval; } xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0; @@ -807,7 +868,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8]) fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; - jtag_add_dr_scan(2, fields, -1, NULL); + jtag_add_dr_scan(2, fields, -1); fields[0].num_bits = 32; fields[0].out_value = packet; @@ -819,7 +880,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8]) { buf_set_u32(packet, 0, 32, buffer[word]); cmd = parity(*((u32*)packet)); - jtag_add_dr_scan(2, fields, -1, NULL); + jtag_add_dr_scan(2, fields, -1); } jtag_execute_queue(); @@ -865,7 +926,7 @@ int xscale_invalidate_ic_line(target_t *target, u32 va) fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; - jtag_add_dr_scan(2, fields, -1, NULL); + jtag_add_dr_scan(2, fields, -1); return ERROR_OK; } @@ -926,7 +987,7 @@ int xscale_update_vectors(target_t *target) return ERROR_OK; } -int xscale_arch_state(struct target_s *target, char *buf, int buf_size) +int xscale_arch_state(struct target_s *target) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -947,8 +1008,7 @@ int xscale_arch_state(struct target_s *target, char *buf, int buf_size) exit(-1); } - snprintf(buf, buf_size, - "target halted in %s state due to %s, current mode: %s\n" + USER("target halted in %s state due to %s, current mode: %s\n" "cpsr: 0x%8.8x pc: 0x%8.8x\n" "MMU: %s, D-Cache: %s, I-Cache: %s" "%s", @@ -965,17 +1025,17 @@ int xscale_arch_state(struct target_s *target, char *buf, int buf_size) return ERROR_OK; } -enum target_state xscale_poll(target_t *target) +int xscale_poll(target_t *target) { - int retval; + int retval=ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING)) { + enum target_state previous_state = target->state; if ((retval = xscale_read_tx(target, 0)) == ERROR_OK) { - enum target_state previous_state = target->state; /* there's data to read from the tx register, we entered debug state */ xscale->handler_running = 1; @@ -983,30 +1043,30 @@ enum target_state xscale_poll(target_t *target) target->state = TARGET_HALTED; /* process debug entry, fetching current mode regs */ - if ((retval = xscale_debug_entry(target)) != ERROR_OK) - return retval; - - /* debug_entry could have overwritten target state (i.e. immediate resume) - * don't signal event handlers in that case - */ - if (target->state != TARGET_HALTED) - return target->state; - - /* if target was running, signal that we halted - * otherwise we reentered from debug execution */ - if (previous_state == TARGET_RUNNING) - target_call_event_callbacks(target, TARGET_EVENT_HALTED); - else - target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED); + retval = xscale_debug_entry(target); } else if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE) { - ERROR("error while polling TX register"); - exit(-1); + USER("error while polling TX register, reset CPU"); + /* here we "lie" so GDB won't get stuck and a reset can be perfomed */ + target->state = TARGET_HALTED; } + + /* debug_entry could have overwritten target state (i.e. immediate resume) + * don't signal event handlers in that case + */ + if (target->state != TARGET_HALTED) + return ERROR_OK; + + /* if target was running, signal that we halted + * otherwise we reentered from debug execution */ + if (previous_state == TARGET_RUNNING) + target_call_event_callbacks(target, TARGET_EVENT_HALTED); + else + target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED); } - return target->state; + return retval; } int xscale_debug_entry(target_t *target) @@ -1014,7 +1074,7 @@ int xscale_debug_entry(target_t *target) armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; u32 pc; - u32 *buffer = malloc(4 * 10); + u32 buffer[10]; int i; u32 moe; @@ -1199,7 +1259,7 @@ int xscale_halt(target_t *target) { /* this must not happen for a xscale target */ ERROR("target was in unknown state when halt was requested"); - exit(-1); + return ERROR_TARGET_INVALID; } else if (target->state == TARGET_RESET) { @@ -1590,7 +1650,7 @@ int xscale_deassert_reset(target_t *target) jtag_add_reset(0, 0); /* wait 300ms; 150 and 100ms were not enough */ - jtag_add_sleep(3000000); + jtag_add_sleep(300*1000); jtag_add_runtest(2030, TAP_RTI); jtag_execute_queue(); @@ -1601,9 +1661,8 @@ int xscale_deassert_reset(target_t *target) xscale_write_dcsr(target, 1, 0); /* Load debug handler */ - if (fileio_open(&debug_handler, PKGLIBDIR "/xscale/debug_handler.bin", FILEIO_READ, FILEIO_BINARY) != ERROR_OK) + if (fileio_open(&debug_handler, "xscale/debug_handler.bin", FILEIO_READ, FILEIO_BINARY) != ERROR_OK) { - ERROR("file open error: %s", debug_handler.error_str); return ERROR_OK; } @@ -1629,7 +1688,7 @@ int xscale_deassert_reset(target_t *target) if ((retval = fileio_read(&debug_handler, 32, buffer, &buf_cnt)) != ERROR_OK) { - ERROR("reading debug handler failed: %s", debug_handler.error_str); + } for (i = 0; i < buf_cnt; i += 4) @@ -1680,6 +1739,8 @@ int xscale_deassert_reset(target_t *target) /* resume the target */ xscale_resume(target, 1, 0x0, 1, 0); } + + fileio_close(&debug_handler); } else { @@ -2006,9 +2067,7 @@ int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 coun int xscale_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer) { - xscale_write_memory(target, address, 4, count, buffer); - - return ERROR_OK; + return xscale_write_memory(target, address, 4, count, buffer); } int xscale_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum) @@ -2267,7 +2326,7 @@ int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - u8 enable; + u8 enable=0; reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON]; u32 dbcon_value = buf_get_u32(dbcon->value, 0, 32); @@ -3073,6 +3132,8 @@ int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, int chain_p xscale->armv4_5_mmu.enable_mmu_caches = xscale_enable_mmu_caches; xscale->armv4_5_mmu.has_tiny_pages = 1; xscale->armv4_5_mmu.mmu_enabled = 0; + + xscale->fast_memory_access = 0; return ERROR_OK; } @@ -3087,7 +3148,7 @@ int xscale_target_command(struct command_context_s *cmd_ctx, char *cmd, char **a if (argc < 5) { ERROR("'target xscale' requires four arguments: "); - exit(-1); + return ERROR_OK; } chain_pos = strtoul(args[3], NULL, 0); @@ -3122,7 +3183,6 @@ int xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, char if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) { - command_print(cmd_ctx, "target isn't an ARM920t target"); return ERROR_OK; } @@ -3163,7 +3223,6 @@ int xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx, if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) { - command_print(cmd_ctx, "target isn't an XScale target"); return ERROR_OK; } @@ -3189,34 +3248,51 @@ int xscale_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cm if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) { - command_print(cmd_ctx, "target isn't an XScale target"); return ERROR_OK; } return armv4_5_handle_cache_info_command(cmd_ctx, &xscale->armv4_5_mmu.armv4_5_cache); } -int xscale_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) +static int xscale_virt2phys(struct target_s *target, u32 virtual, u32 *physical) { - target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; xscale_common_t *xscale; - - if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) + int retval; + int type; + u32 cb; + int domain; + u32 ap; + + + if ((retval = xscale_get_arch_pointers(target, &armv4_5, &xscale)) != ERROR_OK) { - command_print(cmd_ctx, "target isn't an XScale target"); - return ERROR_OK; + return retval; + } + u32 ret = armv4_5_mmu_translate_va(target, &xscale->armv4_5_mmu, virtual, &type, &cb, &domain, &ap); + if (type == -1) + { + return ret; } + *physical = ret; + return ERROR_OK; +} +static int xscale_mmu(struct target_s *target, int *enabled) +{ + armv4_5_common_t *armv4_5 = target->arch_info; + xscale_common_t *xscale = armv4_5->arch_info; + if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); - return ERROR_OK; + ERROR("Target not halted"); + return ERROR_TARGET_INVALID; } - - return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &xscale->armv4_5_mmu); + *enabled = xscale->armv4_5_mmu.mmu_enabled; + return ERROR_OK; } + int xscale_handle_mmu_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); @@ -3225,7 +3301,6 @@ int xscale_handle_mmu_command(command_context_t *cmd_ctx, char *cmd, char **args if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) { - command_print(cmd_ctx, "target isn't an XScale target"); return ERROR_OK; } @@ -3263,7 +3338,6 @@ int xscale_handle_idcache_command(command_context_t *cmd_ctx, char *cmd, char ** if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) { - command_print(cmd_ctx, "target isn't an XScale target"); return ERROR_OK; } @@ -3317,7 +3391,6 @@ int xscale_handle_vector_catch_command(command_context_t *cmd_ctx, char *cmd, ch if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) { - command_print(cmd_ctx, "target isn't an XScale target"); return ERROR_OK; } @@ -3345,7 +3418,6 @@ int xscale_handle_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) { - command_print(cmd_ctx, "target isn't an XScale target"); return ERROR_OK; } @@ -3376,7 +3448,6 @@ int xscale_handle_trace_buffer_command(struct command_context_s *cmd_ctx, char * if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) { - command_print(cmd_ctx, "target isn't an XScale target"); return ERROR_OK; } @@ -3463,7 +3534,6 @@ int xscale_handle_trace_image_command(struct command_context_s *cmd_ctx, char *c if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) { - command_print(cmd_ctx, "target isn't an XScale target"); return ERROR_OK; } @@ -3491,7 +3561,6 @@ int xscale_handle_trace_image_command(struct command_context_s *cmd_ctx, char *c if (image_open(xscale->trace.image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK) { - command_print(cmd_ctx, "image opening error: %s", xscale->trace.image->error_str); free(xscale->trace.image); xscale->trace.image = NULL; return ERROR_OK; @@ -3510,7 +3579,6 @@ int xscale_handle_dump_trace_command(struct command_context_s *cmd_ctx, char *cm if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) { - command_print(cmd_ctx, "target isn't an XScale target"); return ERROR_OK; } @@ -3536,7 +3604,6 @@ int xscale_handle_dump_trace_command(struct command_context_s *cmd_ctx, char *cm if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK) { - command_print(cmd_ctx, "file open error: %s", file.error_str); return ERROR_OK; } @@ -3568,7 +3635,6 @@ int xscale_handle_analyze_trace_buffer_command(struct command_context_s *cmd_ctx if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) { - command_print(cmd_ctx, "target isn't an XScale target"); return ERROR_OK; } @@ -3577,17 +3643,140 @@ int xscale_handle_analyze_trace_buffer_command(struct command_context_s *cmd_ctx return ERROR_OK; } +int xscale_handle_cp15(command_context_t *cmd_ctx, char *cmd, char **args, int argc) +{ + target_t *target = get_current_target(cmd_ctx); + armv4_5_common_t *armv4_5; + xscale_common_t *xscale; + + if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) + { + return ERROR_OK; + } + + if (target->state != TARGET_HALTED) + { + command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); + return ERROR_OK; + } + u32 reg_no = 0; + reg_t *reg = NULL; + if(argc > 0) + { + reg_no = strtoul(args[0], NULL, 0); + /*translate from xscale cp15 register no to openocd register*/ + switch(reg_no) + { + case 0: + reg_no = XSCALE_MAINID; + break; + case 1: + reg_no = XSCALE_CTRL; + break; + case 2: + reg_no = XSCALE_TTB; + break; + case 3: + reg_no = XSCALE_DAC; + break; + case 5: + reg_no = XSCALE_FSR; + break; + case 6: + reg_no = XSCALE_FAR; + break; + case 13: + reg_no = XSCALE_PID; + break; + case 15: + reg_no = XSCALE_CPACCESS; + break; + default: + command_print(cmd_ctx, "invalid register number"); + return ERROR_INVALID_ARGUMENTS; + } + reg = &xscale->reg_cache->reg_list[reg_no]; + + } + if(argc == 1) + { + u32 value; + + /* read cp15 control register */ + xscale_get_reg(reg); + value = buf_get_u32(reg->value, 0, 32); + command_print(cmd_ctx, "%s (/%i): 0x%x", reg->name, reg->size, value); + } + else if(argc == 2) + { + + u32 value = strtoul(args[1], NULL, 0); + + /* send CP write request (command 0x41) */ + xscale_send_u32(target, 0x41); + + /* send CP register number */ + xscale_send_u32(target, reg_no); + + /* send CP register value */ + xscale_send_u32(target, value); + + /* execute cpwait to ensure outstanding operations complete */ + xscale_send_u32(target, 0x53); + } + else + { + command_print(cmd_ctx, "usage: cp15 [register]<, [value]>"); + } + + return ERROR_OK; +} + +int handle_xscale_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +{ + target_t *target = get_current_target(cmd_ctx); + armv4_5_common_t *armv4_5; + xscale_common_t *xscale; + + if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) + { + return ERROR_OK; + } + + if (argc == 1) + { + if (strcmp("enable", args[0]) == 0) + { + xscale->fast_memory_access = 1; + } + else if (strcmp("disable", args[0]) == 0) + { + xscale->fast_memory_access = 0; + } + else + { + return ERROR_COMMAND_SYNTAX_ERROR; + } + } else if (argc!=0) + { + return ERROR_COMMAND_SYNTAX_ERROR; + } + + command_print(cmd_ctx, "fast memory access is %s", (xscale->fast_memory_access) ? "enabled" : "disabled"); + + return ERROR_OK; +} + int xscale_register_commands(struct command_context_s *cmd_ctx) { command_t *xscale_cmd; xscale_cmd = register_command(cmd_ctx, NULL, "xscale", NULL, COMMAND_ANY, "xscale specific commands"); - register_command(cmd_ctx, xscale_cmd, "debug_handler", xscale_handle_debug_handler_command, COMMAND_CONFIG, NULL); + register_command(cmd_ctx, xscale_cmd, "debug_handler", xscale_handle_debug_handler_command, COMMAND_ANY, "'xscale debug_handler
' command takes two required operands"); register_command(cmd_ctx, xscale_cmd, "cache_clean_address", xscale_handle_cache_clean_address_command, COMMAND_ANY, NULL); register_command(cmd_ctx, xscale_cmd, "cache_info", xscale_handle_cache_info_command, COMMAND_EXEC, NULL); - register_command(cmd_ctx, xscale_cmd, "virt2phys", xscale_handle_virt2phys_command, COMMAND_EXEC, NULL); register_command(cmd_ctx, xscale_cmd, "mmu", xscale_handle_mmu_command, COMMAND_EXEC, "['enable'|'disable'] the MMU"); register_command(cmd_ctx, xscale_cmd, "icache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the ICache"); register_command(cmd_ctx, xscale_cmd, "dcache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the DCache"); @@ -3601,6 +3790,11 @@ int xscale_register_commands(struct command_context_s *cmd_ctx) register_command(cmd_ctx, xscale_cmd, "trace_image", xscale_handle_trace_image_command, COMMAND_EXEC, "load image from [base address]"); + register_command(cmd_ctx, xscale_cmd, "cp15", xscale_handle_cp15, COMMAND_EXEC, "access coproc 15 [value]"); + register_command(cmd_ctx, xscale_cmd, "fast_memory_access", handle_xscale_fast_memory_access_command, + COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses "); + + armv4_5_register_commands(cmd_ctx); return ERROR_OK;