X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fxscale.c;h=d776e2107d200cd730427737a40900b76f4f9a61;hp=921af812b9591d77dafe6bd893b5172cbe7fe4d1;hb=dfbb9f3e89ae;hpb=09e303bb8e51f0ab123c70f954039fbef8ca9a91 diff --git a/src/target/xscale.c b/src/target/xscale.c index 921af812b9..d776e2107d 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -25,6 +25,7 @@ #include "xscale.h" +#include "arm7_9_common.h" #include "register.h" #include "target.h" #include "armv4_5.h" @@ -64,7 +65,6 @@ int xscale_restore_context(target_t *target); int xscale_assert_reset(target_t *target); int xscale_deassert_reset(target_t *target); int xscale_soft_reset_halt(struct target_s *target); -int xscale_prepare_reset_halt(struct target_s *target); int xscale_set_reg_u32(reg_t *reg, u32 value); @@ -74,7 +74,6 @@ int xscale_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); int xscale_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer); -int xscale_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum); int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint); int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint); @@ -105,15 +104,15 @@ target_type_t xscale_target = .assert_reset = xscale_assert_reset, .deassert_reset = xscale_deassert_reset, .soft_reset_halt = xscale_soft_reset_halt, - .prepare_reset_halt = xscale_prepare_reset_halt, .get_gdb_reg_list = armv4_5_get_gdb_reg_list, .read_memory = xscale_read_memory, .write_memory = xscale_write_memory, .bulk_write_memory = xscale_bulk_write_memory, - .checksum_memory = xscale_checksum_memory, - + .checksum_memory = arm7_9_checksum_memory, + .blank_check_memory = arm7_9_blank_check_memory, + .run_algorithm = armv4_5_run_algorithm, .add_breakpoint = xscale_add_breakpoint, @@ -194,13 +193,13 @@ int xscale_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, xsc if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { - ERROR("target isn't an XScale target"); + LOG_ERROR("target isn't an XScale target"); return -1; } if (xscale->common_magic != XSCALE_COMMON_MAGIC) { - ERROR("target isn't an XScale target"); + LOG_ERROR("target isn't an XScale target"); return -1; } @@ -283,7 +282,7 @@ int xscale_read_dcsr(target_t *target) if ((retval = jtag_execute_queue()) != ERROR_OK) { - ERROR("JTAG error while reading DCSR"); + LOG_ERROR("JTAG error while reading DCSR"); return retval; } @@ -382,7 +381,7 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) if ((retval = jtag_execute_queue()) != ERROR_OK) { - ERROR("JTAG error while receiving data from debug handler"); + LOG_ERROR("JTAG error while receiving data from debug handler"); break; } @@ -405,7 +404,7 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) { if (attempts++==1000) { - ERROR("Failed to receiving data from debug handler after 1000 attempts"); + LOG_ERROR("Failed to receiving data from debug handler after 1000 attempts"); retval=ERROR_TARGET_TIMEOUT; break; } @@ -427,7 +426,7 @@ int xscale_read_tx(target_t *target, int consume) armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; enum tap_state path[3]; - enum tap_state noconsume_path[9]; + enum tap_state noconsume_path[6]; int retval; struct timeval timeout, now; @@ -452,10 +451,7 @@ int xscale_read_tx(target_t *target, int consume) noconsume_path[2] = TAP_E1D; noconsume_path[3] = TAP_PD; noconsume_path[4] = TAP_E2D; - noconsume_path[5] = TAP_UD; - noconsume_path[6] = TAP_SDS; - noconsume_path[7] = TAP_CD; - noconsume_path[8] = TAP_SD; + noconsume_path[5] = TAP_SD; fields[0].device = xscale->jtag_info.chain_pos; fields[0].num_bits = 3; @@ -484,39 +480,47 @@ int xscale_read_tx(target_t *target, int consume) jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL); gettimeofday(&timeout, NULL); - timeval_add_time(&timeout, 5, 0); + timeval_add_time(&timeout, 1, 0); for (;;) { - /* if we want to consume the register content (i.e. clear TX_READY), - * we have to go straight from Capture-DR to Shift-DR - * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR - */ - if (consume) - jtag_add_pathmove(3, path); - else - jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path); - - jtag_add_dr_scan(3, fields, TAP_RTI); - - if ((retval = jtag_execute_queue()) != ERROR_OK) - { - ERROR("JTAG error while reading TX"); - return ERROR_TARGET_TIMEOUT; - } - - gettimeofday(&now, NULL); - if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec))) - { - ERROR("time out reading TX register"); - return ERROR_TARGET_TIMEOUT; - } - if (!((!(field0_in & 1)) && consume)) + int i; + for (i=0; i<100; i++) { - break; + /* if we want to consume the register content (i.e. clear TX_READY), + * we have to go straight from Capture-DR to Shift-DR + * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR + */ + if (consume) + jtag_add_pathmove(3, path); + else + { + jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path); + } + + jtag_add_dr_scan(3, fields, TAP_RTI); + + if ((retval = jtag_execute_queue()) != ERROR_OK) + { + LOG_ERROR("JTAG error while reading TX"); + return ERROR_TARGET_TIMEOUT; + } + + gettimeofday(&now, NULL); + if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec))) + { + LOG_ERROR("time out reading TX register"); + return ERROR_TARGET_TIMEOUT; + } + if (!((!(field0_in & 1)) && consume)) + { + goto done; + } } - usleep(500*1000); /* avoid flooding the logs */ + LOG_DEBUG("waiting 10ms"); + usleep(10*1000); /* avoid flooding the logs */ } + done: if (!(field0_in & 1)) return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; @@ -572,38 +576,44 @@ int xscale_write_rx(target_t *target) jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL); gettimeofday(&timeout, NULL); - timeval_add_time(&timeout, 5, 0); + timeval_add_time(&timeout, 1, 0); /* poll until rx_read is low */ - DEBUG("polling RX"); + LOG_DEBUG("polling RX"); for (;;) { - jtag_add_dr_scan(3, fields, TAP_RTI); - - if ((retval = jtag_execute_queue()) != ERROR_OK) - { - ERROR("JTAG error while writing RX"); - return retval; - } - - gettimeofday(&now, NULL); - if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec))) + int i; + for (i=0; i<10; i++) { - ERROR("time out writing RX register"); - return ERROR_TARGET_TIMEOUT; + jtag_add_dr_scan(3, fields, TAP_RTI); + + if ((retval = jtag_execute_queue()) != ERROR_OK) + { + LOG_ERROR("JTAG error while writing RX"); + return retval; + } + + gettimeofday(&now, NULL); + if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec))) + { + LOG_ERROR("time out writing RX register"); + return ERROR_TARGET_TIMEOUT; + } + if (!(field0_in & 1)) + goto done; } - if (!(field0_in & 1)) - break; - usleep(500*1000); /* wait 500ms to avoid flooding the logs */ + LOG_DEBUG("waiting 10ms"); + usleep(10*1000); /* wait 10ms to avoid flooding the logs */ } - + done: + /* set rx_valid */ field2 = 0x1; jtag_add_dr_scan(3, fields, TAP_RTI); if ((retval = jtag_execute_queue()) != ERROR_OK) { - ERROR("JTAG error while writing RX"); + LOG_ERROR("JTAG error while writing RX"); return retval; } @@ -615,109 +625,63 @@ int xscale_send(target_t *target, u8 *buffer, int count, int size) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; + u32 t[3]; + int bits[3]; int retval; int done_count = 0; - u8 output[4] = {0, 0, 0, 0}; - - scan_field_t fields[3]; - u8 field0_out = 0x0; - u8 field0_check_value = 0x2; - u8 field0_check_mask = 0x6; - u8 field2 = 0x1; - u8 field2_check_value = 0x0; - u8 field2_check_mask = 0x1; - + jtag_add_end_state(TAP_RTI); xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgrx); - fields[0].device = xscale->jtag_info.chain_pos; - fields[0].num_bits = 3; - fields[0].out_value = &field0_out; - fields[0].out_mask = NULL; - fields[0].in_handler = NULL; - fields[0].in_value = NULL; - if (!xscale->fast_memory_access) - { - jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL); - } - - fields[1].device = xscale->jtag_info.chain_pos; - fields[1].num_bits = 32; - fields[1].out_value = output; - fields[1].out_mask = NULL; - fields[1].in_value = NULL; - fields[1].in_handler = NULL; - fields[1].in_handler_priv = NULL; - fields[1].in_check_value = NULL; - fields[1].in_check_mask = NULL; - - - - fields[2].device = xscale->jtag_info.chain_pos; - fields[2].num_bits = 1; - fields[2].out_value = &field2; - fields[2].out_mask = NULL; - fields[2].in_value = NULL; - fields[2].in_handler = NULL; - if (!xscale->fast_memory_access) + bits[0]=3; + t[0]=0; + bits[1]=32; + t[2]=1; + bits[2]=1; + int endianness = target->endianness; + while (done_count++ < count) { - jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL); - } - - if (size==4) - { - int endianness = target->endianness; - while (done_count++ < count) + switch (size) { + case 4: if (endianness == TARGET_LITTLE_ENDIAN) { - output[0]=buffer[0]; - output[1]=buffer[1]; - output[2]=buffer[2]; - output[3]=buffer[3]; + t[1]=le_to_h_u32(buffer); } else { - output[0]=buffer[3]; - output[1]=buffer[2]; - output[2]=buffer[1]; - output[3]=buffer[0]; + t[1]=be_to_h_u32(buffer); } - jtag_add_dr_scan(3, fields, TAP_RTI); - buffer += size; - } - - } else - { - while (done_count++ < count) - { - /* extract sized element from target-endian buffer, and put it - * into little-endian output buffer - */ - switch (size) + break; + case 2: + if (endianness == TARGET_LITTLE_ENDIAN) { - case 2: - buf_set_u32(output, 0, 32, target_buffer_get_u16(target, buffer)); - break; - case 1: - output[0] = *buffer; - break; - default: - ERROR("BUG: size neither 4, 2 nor 1"); - exit(-1); + t[1]=le_to_h_u16(buffer); + } else + { + t[1]=be_to_h_u16(buffer); } - - jtag_add_dr_scan(3, fields, TAP_RTI); - buffer += size; + break; + case 1: + t[1]=buffer[0]; + break; + default: + LOG_ERROR("BUG: size neither 4, 2 nor 1"); + exit(-1); } - + jtag_add_dr_out(xscale->jtag_info.chain_pos, + 3, + bits, + t, + TAP_RTI); + buffer += size; } if ((retval = jtag_execute_queue()) != ERROR_OK) { - ERROR("JTAG error while sending data to debug handler"); + LOG_ERROR("JTAG error while sending data to debug handler"); return retval; } @@ -790,7 +754,7 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) if ((retval = jtag_execute_queue()) != ERROR_OK) { - ERROR("JTAG error while writing DCSR"); + LOG_ERROR("JTAG error while writing DCSR"); return retval; } @@ -808,7 +772,7 @@ unsigned int parity (unsigned int v) v ^= v >> 8; v ^= v >> 4; v &= 0xf; - DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1); + LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1); return (0x6996 >> v) & 1; } @@ -822,7 +786,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8]) scan_field_t fields[2]; - DEBUG("loading miniIC at 0x%8.8x", va); + LOG_DEBUG("loading miniIC at 0x%8.8x", va); jtag_add_end_state(TAP_RTI); xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.ldic); /* LDIC */ @@ -1003,11 +967,11 @@ int xscale_arch_state(struct target_s *target) if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { - ERROR("BUG: called for a non-ARMv4/5 target"); + LOG_ERROR("BUG: called for a non-ARMv4/5 target"); exit(-1); } - USER("target halted in %s state due to %s, current mode: %s\n" + LOG_USER("target halted in %s state due to %s, current mode: %s\n" "cpsr: 0x%8.8x pc: 0x%8.8x\n" "MMU: %s, D-Cache: %s, I-Cache: %s" "%s", @@ -1046,7 +1010,7 @@ int xscale_poll(target_t *target) } else if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE) { - USER("error while polling TX register, reset CPU"); + LOG_USER("error while polling TX register, reset CPU"); /* here we "lie" so GDB won't get stuck and a reset can be perfomed */ target->state = TARGET_HALTED; } @@ -1092,13 +1056,13 @@ int xscale_debug_entry(target_t *target) buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, buffer[0]); armv4_5->core_cache->reg_list[15].dirty = 1; armv4_5->core_cache->reg_list[15].valid = 1; - DEBUG("r0: 0x%8.8x", buffer[0]); + LOG_DEBUG("r0: 0x%8.8x", buffer[0]); /* move pc from buffer to register cache */ buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, buffer[1]); armv4_5->core_cache->reg_list[15].dirty = 1; armv4_5->core_cache->reg_list[15].valid = 1; - DEBUG("pc: 0x%8.8x", buffer[1]); + LOG_DEBUG("pc: 0x%8.8x", buffer[1]); /* move data from buffer to register cache */ for (i = 1; i <= 7; i++) @@ -1106,28 +1070,32 @@ int xscale_debug_entry(target_t *target) buf_set_u32(armv4_5->core_cache->reg_list[i].value, 0, 32, buffer[1 + i]); armv4_5->core_cache->reg_list[i].dirty = 1; armv4_5->core_cache->reg_list[i].valid = 1; - DEBUG("r%i: 0x%8.8x", i, buffer[i + 1]); + LOG_DEBUG("r%i: 0x%8.8x", i, buffer[i + 1]); } buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, buffer[9]); armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; - DEBUG("cpsr: 0x%8.8x", buffer[9]); + LOG_DEBUG("cpsr: 0x%8.8x", buffer[9]); armv4_5->core_mode = buffer[9] & 0x1f; if (armv4_5_mode_to_number(armv4_5->core_mode) == -1) { target->state = TARGET_UNKNOWN; - ERROR("cpsr contains invalid mode value - communication failure"); + LOG_ERROR("cpsr contains invalid mode value - communication failure"); return ERROR_TARGET_FAILURE; } - DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]); + LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]); if (buffer[9] & 0x20) armv4_5->core_state = ARMV4_5_STATE_THUMB; else armv4_5->core_state = ARMV4_5_STATE_ARM; + + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + return ERROR_FAIL; + /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */ if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS)) { @@ -1196,7 +1164,7 @@ int xscale_debug_entry(target_t *target) break; case 0x7: /* Reserved */ default: - ERROR("Method of Entry is 'Reserved'"); + LOG_ERROR("Method of Entry is 'Reserved'"); exit(-1); break; } @@ -1250,22 +1218,22 @@ int xscale_halt(target_t *target) armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", target_state_strings[target->state]); if (target->state == TARGET_HALTED) { - WARNING("target was already halted"); + LOG_DEBUG("target was already halted"); return ERROR_OK; } else if (target->state == TARGET_UNKNOWN) { /* this must not happen for a xscale target */ - ERROR("target was in unknown state when halt was requested"); + LOG_ERROR("target was in unknown state when halt was requested"); return ERROR_TARGET_INVALID; } else if (target->state == TARGET_RESET) { - DEBUG("target->state == TARGET_RESET"); + LOG_DEBUG("target->state == TARGET_RESET"); } else { @@ -1295,7 +1263,7 @@ int xscale_enable_single_step(struct target_s *target, u32 next_pc) } else { - ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found"); + LOG_ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found"); exit(-1); } } @@ -1327,11 +1295,11 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_ int retval; int i; - DEBUG("-"); + LOG_DEBUG("-"); if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1365,7 +1333,7 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_ u32 next_pc; /* there's a breakpoint at the current PC, we have to step over it */ - DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address); + LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address); xscale_unset_breakpoint(target, breakpoint); /* calculate PC of next instruction */ @@ -1373,10 +1341,10 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_ { u32 current_opcode; target_read_u32(target, current_pc, ¤t_opcode); - ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode); + LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode); } - DEBUG("enable single-step"); + LOG_DEBUG("enable single-step"); xscale_enable_single_step(target, next_pc); /* restore banked registers */ @@ -1394,26 +1362,26 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_ /* send CPSR */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); - DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); + LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); for (i = 7; i >= 0; i--) { /* send register */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); - DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); + LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); } /* send PC */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); - DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); + LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); /* wait for and process debug entry */ xscale_debug_entry(target); - DEBUG("disable single-step"); + LOG_DEBUG("disable single-step"); xscale_disable_single_step(target); - DEBUG("set breakpoint at 0x%8.8x", breakpoint->address); + LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address); xscale_set_breakpoint(target, breakpoint); } } @@ -1437,18 +1405,18 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_ /* send CPSR */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); - DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); + LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); for (i = 7; i >= 0; i--) { /* send register */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); - DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); + LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); } /* send PC */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); - DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); + LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); target->debug_reason = DBG_REASON_NOTHALTED; @@ -1465,7 +1433,7 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_ target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED); } - DEBUG("target resumed"); + LOG_DEBUG("target resumed"); xscale->handler_running = 1; @@ -1484,7 +1452,7 @@ int xscale_step(struct target_s *target, int current, u32 address, int handle_br if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1520,10 +1488,10 @@ int xscale_step(struct target_s *target, int current, u32 address, int handle_br { u32 current_opcode; target_read_u32(target, current_pc, ¤t_opcode); - ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode); + LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode); } - DEBUG("enable single-step"); + LOG_DEBUG("enable single-step"); xscale_enable_single_step(target, next_pc); /* restore banked registers */ @@ -1541,18 +1509,18 @@ int xscale_step(struct target_s *target, int current, u32 address, int handle_br /* send CPSR */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); - DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); + LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); for (i = 7; i >= 0; i--) { /* send register */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); - DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); + LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); } /* send PC */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); - DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); + LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); target_call_event_callbacks(target, TARGET_EVENT_RESUMED); @@ -1562,7 +1530,7 @@ int xscale_step(struct target_s *target, int current, u32 address, int handle_br /* wait for and process debug entry */ xscale_debug_entry(target); - DEBUG("disable single-step"); + LOG_DEBUG("disable single-step"); xscale_disable_single_step(target); target_call_event_callbacks(target, TARGET_EVENT_HALTED); @@ -1572,7 +1540,7 @@ int xscale_step(struct target_s *target, int current, u32 address, int handle_br xscale_set_breakpoint(target, breakpoint); } - DEBUG("target stepped"); + LOG_DEBUG("target stepped"); return ERROR_OK; @@ -1583,7 +1551,7 @@ int xscale_assert_reset(target_t *target) armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", target_state_strings[target->state]); /* select DCSR instruction (set endstate to R-T-I to ensure we don't * end up in T-L-R, which would reset JTAG @@ -1627,7 +1595,7 @@ int xscale_deassert_reset(target_t *target) breakpoint_t *breakpoint = target->breakpoints; - DEBUG("-"); + LOG_DEBUG("-"); xscale->ibcr_available = 2; xscale->ibcr0_used = 0; @@ -1671,13 +1639,13 @@ int xscale_deassert_reset(target_t *target) if ((binary_size = debug_handler.size) % 4) { - ERROR("debug_handler.bin: size not a multiple of 4"); + LOG_ERROR("debug_handler.bin: size not a multiple of 4"); exit(-1); } if (binary_size > 0x800) { - ERROR("debug_handler.bin: larger than 2kb"); + LOG_ERROR("debug_handler.bin: larger than 2kb"); exit(-1); } @@ -1731,7 +1699,7 @@ int xscale_deassert_reset(target_t *target) xscale_write_dcsr(target, 0, 1); target->state = TARGET_RUNNING; - if ((target->reset_mode != RESET_HALT) && (target->reset_mode != RESET_INIT)) + if (!target->reset_halt) { jtag_add_sleep(10000); @@ -1760,14 +1728,6 @@ int xscale_soft_reset_halt(struct target_s *target) return ERROR_OK; } -int xscale_prepare_reset_halt(struct target_s *target) -{ - /* nothing to be done for reset_halt on XScale targets - * we always halt after a reset to upload the debug handler - */ - return ERROR_OK; -} - int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode) { @@ -1788,11 +1748,11 @@ int xscale_full_context(target_t *target) int i, j; - DEBUG("-"); + LOG_DEBUG("-"); if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1862,11 +1822,11 @@ int xscale_restore_context(target_t *target) int i, j; - DEBUG("-"); + LOG_DEBUG("-"); if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1933,11 +1893,11 @@ int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count int i; int retval; - DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count); + LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count); if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1982,7 +1942,7 @@ int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count *buffer++ = buf32[i] & 0xff; break; default: - ERROR("should never get here"); + LOG_ERROR("should never get here"); exit(-1); } } @@ -2010,11 +1970,11 @@ int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 coun xscale_common_t *xscale = armv4_5->arch_info; int retval; - DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count); + LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count); if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2059,7 +2019,7 @@ int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 coun buffer += 1; break; default: - ERROR("should never get here"); + LOG_ERROR("should never get here"); exit(-1); } } @@ -2087,11 +2047,6 @@ int xscale_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe return xscale_write_memory(target, address, 4, count, buffer); } -int xscale_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum) -{ - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; -} - u32 xscale_get_ttb(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; @@ -2176,7 +2131,7 @@ int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2185,7 +2140,7 @@ int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (breakpoint->set) { - WARNING("breakpoint already set"); + LOG_WARNING("breakpoint already set"); return ERROR_OK; } @@ -2206,7 +2161,7 @@ int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) } else { - ERROR("BUG: no hardware comparator available"); + LOG_ERROR("BUG: no hardware comparator available"); return ERROR_OK; } } @@ -2240,19 +2195,19 @@ int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } if (xscale->force_hw_bkpts) { - DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address); + LOG_DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address); breakpoint->type = BKPT_HARD; } if ((breakpoint->type == BKPT_HARD) && (xscale->ibcr_available < 1)) { - INFO("no breakpoint unit available for hardware breakpoint"); + LOG_INFO("no breakpoint unit available for hardware breakpoint"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } else @@ -2262,7 +2217,7 @@ int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if ((breakpoint->length != 2) && (breakpoint->length != 4)) { - INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported"); + LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -2276,13 +2231,13 @@ int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } if (!breakpoint->set) { - WARNING("breakpoint not set"); + LOG_WARNING("breakpoint not set"); return ERROR_OK; } @@ -2324,7 +2279,7 @@ int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2349,7 +2304,7 @@ int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2367,7 +2322,7 @@ int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) enable = 0x1; break; default: - ERROR("BUG: watchpoint->rw neither read, write nor access"); + LOG_ERROR("BUG: watchpoint->rw neither read, write nor access"); } if (!xscale->dbr0_used) @@ -2388,7 +2343,7 @@ int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) } else { - ERROR("BUG: no hardware comparator available"); + LOG_ERROR("BUG: no hardware comparator available"); return ERROR_OK; } @@ -2402,7 +2357,7 @@ int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2430,13 +2385,13 @@ int xscale_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } if (!watchpoint->set) { - WARNING("breakpoint not set"); + LOG_WARNING("breakpoint not set"); return ERROR_OK; } @@ -2464,7 +2419,7 @@ int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2642,7 +2597,7 @@ int xscale_read_trace(target_t *target) if (target->state != TARGET_HALTED) { - WARNING("target must be stopped to read trace data"); + LOG_WARNING("target must be stopped to read trace data"); return ERROR_TARGET_NOT_HALTED; } @@ -2677,7 +2632,7 @@ int xscale_read_trace(target_t *target) if (j == 256) { - DEBUG("no trace data collected"); + LOG_DEBUG("no trace data collected"); return ERROR_XSCALE_NO_TRACE_DATA; } @@ -2742,7 +2697,7 @@ int xscale_read_instruction(target_t *target, arm_instruction_t *instruction) xscale->trace.current_pc - xscale->trace.image->sections[section].base_address, 4, buf, &size_read)) != ERROR_OK) { - ERROR("error while reading instruction: %i", retval); + LOG_ERROR("error while reading instruction: %i", retval); return ERROR_TRACE_INSTRUCTION_UNAVAILABLE; } opcode = target_buffer_get_u32(target, buf); @@ -2755,7 +2710,7 @@ int xscale_read_instruction(target_t *target, arm_instruction_t *instruction) xscale->trace.current_pc - xscale->trace.image->sections[section].base_address, 2, buf, &size_read)) != ERROR_OK) { - ERROR("error while reading instruction: %i", retval); + LOG_ERROR("error while reading instruction: %i", retval); return ERROR_TRACE_INSTRUCTION_UNAVAILABLE; } opcode = target_buffer_get_u16(target, buf); @@ -2763,7 +2718,7 @@ int xscale_read_instruction(target_t *target, arm_instruction_t *instruction) } else { - ERROR("BUG: unknown core state encountered"); + LOG_ERROR("BUG: unknown core state encountered"); exit(-1); } @@ -2846,7 +2801,7 @@ int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx) next_pc_ok = 1; if (((chkpt == 0) && (next_pc != trace_data->chkpt0)) || ((chkpt == 1) && (next_pc != trace_data->chkpt1))) - WARNING("checkpointed indirect branch target address doesn't match checkpoint"); + LOG_WARNING("checkpointed indirect branch target address doesn't match checkpoint"); } /* explicit fall-through */ case 12: /* Checkpointed Direct Branch */ @@ -2865,7 +2820,7 @@ int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx) } else { - WARNING("more than two checkpointed branches encountered"); + LOG_WARNING("more than two checkpointed branches encountered"); } break; case 15: /* Roll-over */ @@ -2873,7 +2828,7 @@ int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx) continue; default: /* Reserved */ command_print(cmd_ctx, "--- reserved trace message ---"); - ERROR("BUG: trace message %i is reserved", (trace_data->entries[i].data & 0xf0) >> 4); + LOG_ERROR("BUG: trace message %i is reserved", (trace_data->entries[i].data & 0xf0) >> 4); return ERROR_OK; } @@ -3021,18 +2976,6 @@ void xscale_build_reg_cache(target_t *target) int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *target) { - if (startup_mode != DAEMON_RESET) - { - ERROR("XScale target requires a reset"); - ERROR("Reset target to enable debug"); - } - - /* assert TRST once during startup */ - jtag_add_reset(1, 0); - jtag_add_sleep(5000); - jtag_add_reset(0, 0); - jtag_execute_queue(); - return ERROR_OK; } @@ -3149,8 +3092,6 @@ int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, int chain_p xscale->armv4_5_mmu.has_tiny_pages = 1; xscale->armv4_5_mmu.mmu_enabled = 0; - xscale->fast_memory_access = 0; - return ERROR_OK; } @@ -3164,7 +3105,7 @@ int xscale_target_command(struct command_context_s *cmd_ctx, char *cmd, char **a if (argc < 5) { - ERROR("'target xscale' requires four arguments: "); + LOG_ERROR("'target xscale' requires four arguments: "); return ERROR_OK; } @@ -3188,13 +3129,13 @@ int xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, char if (argc < 2) { - ERROR("'xscale debug_handler
' command takes two required operands"); + LOG_ERROR("'xscale debug_handler
' command takes two required operands"); return ERROR_OK; } if ((target = get_target_by_num(strtoul(args[0], NULL, 0))) == NULL) { - ERROR("no target '%s' configured", args[0]); + LOG_ERROR("no target '%s' configured", args[0]); return ERROR_OK; } @@ -3212,7 +3153,7 @@ int xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, char } else { - ERROR("xscale debug_handler
must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800"); + LOG_ERROR("xscale debug_handler
must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800"); } return ERROR_OK; @@ -3228,13 +3169,13 @@ int xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx, if (argc < 2) { - ERROR("'xscale cache_clean_address
' command takes two required operands"); + LOG_ERROR("'xscale cache_clean_address
' command takes two required operands"); return ERROR_OK; } if ((target = get_target_by_num(strtoul(args[0], NULL, 0))) == NULL) { - ERROR("no target '%s' configured", args[0]); + LOG_ERROR("no target '%s' configured", args[0]); return ERROR_OK; } @@ -3247,7 +3188,7 @@ int xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx, if (cache_clean_address & 0xffff) { - ERROR("xscale cache_clean_address
must be 64kb aligned"); + LOG_ERROR("xscale cache_clean_address
must be 64kb aligned"); } else { @@ -3302,7 +3243,7 @@ static int xscale_mmu(struct target_s *target, int *enabled) if (target->state != TARGET_HALTED) { - ERROR("Target not halted"); + LOG_ERROR("Target not halted"); return ERROR_TARGET_INVALID; } *enabled = xscale->armv4_5_mmu.mmu_enabled; @@ -3749,41 +3690,6 @@ int xscale_handle_cp15(command_context_t *cmd_ctx, char *cmd, char **args, int a return ERROR_OK; } -int handle_xscale_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) -{ - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - xscale_common_t *xscale; - - if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) - { - return ERROR_OK; - } - - if (argc == 1) - { - if (strcmp("enable", args[0]) == 0) - { - xscale->fast_memory_access = 1; - } - else if (strcmp("disable", args[0]) == 0) - { - xscale->fast_memory_access = 0; - } - else - { - return ERROR_COMMAND_SYNTAX_ERROR; - } - } else if (argc!=0) - { - return ERROR_COMMAND_SYNTAX_ERROR; - } - - command_print(cmd_ctx, "fast memory access is %s", (xscale->fast_memory_access) ? "enabled" : "disabled"); - - return ERROR_OK; -} - int xscale_register_commands(struct command_context_s *cmd_ctx) { command_t *xscale_cmd; @@ -3808,9 +3714,6 @@ int xscale_register_commands(struct command_context_s *cmd_ctx) COMMAND_EXEC, "load image from [base address]"); register_command(cmd_ctx, xscale_cmd, "cp15", xscale_handle_cp15, COMMAND_EXEC, "access coproc 15 [value]"); - register_command(cmd_ctx, xscale_cmd, "fast_memory_access", handle_xscale_fast_memory_access_command, - COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses "); - armv4_5_register_commands(cmd_ctx);