X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fxscale.c;h=d776e2107d200cd730427737a40900b76f4f9a61;hp=cb673df686594793b920ba4b3fda22f55f499ef9;hb=dfbb9f3e89ae6a3769d0df2167208c7c07e22e3c;hpb=2e01a1ad1930aabb9e3bc7a0e3eb98b2b3331b1c diff --git a/src/target/xscale.c b/src/target/xscale.c index cb673df686..d776e2107d 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -25,6 +25,7 @@ #include "xscale.h" +#include "arm7_9_common.h" #include "register.h" #include "target.h" #include "armv4_5.h" @@ -53,8 +54,8 @@ int xscale_target_command(struct command_context_s *cmd_ctx, char *cmd, char **a int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *target); int xscale_quit(); -int xscale_arch_state(struct target_s *target, char *buf, int buf_size); -enum target_state xscale_poll(target_t *target); +int xscale_arch_state(struct target_s *target); +int xscale_poll(target_t *target); int xscale_halt(target_t *target); int xscale_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution); int xscale_step(struct target_s *target, int current, u32 address, int handle_breakpoints); @@ -64,7 +65,6 @@ int xscale_restore_context(target_t *target); int xscale_assert_reset(target_t *target); int xscale_deassert_reset(target_t *target); int xscale_soft_reset_halt(struct target_s *target); -int xscale_prepare_reset_halt(struct target_s *target); int xscale_set_reg_u32(reg_t *reg, u32 value); @@ -74,7 +74,6 @@ int xscale_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); int xscale_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer); -int xscale_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum); int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint); int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint); @@ -84,6 +83,8 @@ int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint); int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint); void xscale_enable_watchpoints(struct target_s *target); void xscale_enable_breakpoints(struct target_s *target); +static int xscale_virt2phys(struct target_s *target, u32 virtual, u32 *physical); +static int xscale_mmu(struct target_s *target, int *enabled); int xscale_read_trace(target_t *target); @@ -103,15 +104,15 @@ target_type_t xscale_target = .assert_reset = xscale_assert_reset, .deassert_reset = xscale_deassert_reset, .soft_reset_halt = xscale_soft_reset_halt, - .prepare_reset_halt = xscale_prepare_reset_halt, .get_gdb_reg_list = armv4_5_get_gdb_reg_list, .read_memory = xscale_read_memory, .write_memory = xscale_write_memory, .bulk_write_memory = xscale_bulk_write_memory, - .checksum_memory = xscale_checksum_memory, - + .checksum_memory = arm7_9_checksum_memory, + .blank_check_memory = arm7_9_blank_check_memory, + .run_algorithm = armv4_5_run_algorithm, .add_breakpoint = xscale_add_breakpoint, @@ -122,7 +123,10 @@ target_type_t xscale_target = .register_commands = xscale_register_commands, .target_command = xscale_target_command, .init_target = xscale_init_target, - .quit = xscale_quit + .quit = xscale_quit, + + .virt2phys = xscale_virt2phys, + .mmu = xscale_mmu }; char* xscale_reg_list[] = @@ -189,11 +193,13 @@ int xscale_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, xsc if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { + LOG_ERROR("target isn't an XScale target"); return -1; } if (xscale->common_magic != XSCALE_COMMON_MAGIC) { + LOG_ERROR("target isn't an XScale target"); return -1; } @@ -218,29 +224,10 @@ int xscale_jtag_set_instr(int chain_pos, u32 new_instr) field.out_mask = NULL; field.in_value = NULL; jtag_set_check_value(&field, device->expected, device->expected_mask, NULL); - - jtag_add_ir_scan(1, &field, -1, NULL); - free(field.out_value); - } - - return ERROR_OK; -} + jtag_add_ir_scan(1, &field, -1); -int xscale_jtag_callback(enum jtag_event event, void *priv) -{ - switch (event) - { - case JTAG_TRST_ASSERTED: - break; - case JTAG_TRST_RELEASED: - break; - case JTAG_SRST_ASSERTED: - break; - case JTAG_SRST_RELEASED: - break; - default: - WARNING("unhandled JTAG event"); + free(field.out_value); } return ERROR_OK; @@ -283,8 +270,6 @@ int xscale_read_dcsr(target_t *target) fields[1].in_handler_priv = NULL; fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; - - fields[2].device = xscale->jtag_info.chain_pos; fields[2].num_bits = 1; @@ -293,12 +278,12 @@ int xscale_read_dcsr(target_t *target) fields[2].in_value = NULL; jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL); - jtag_add_dr_scan(3, fields, -1, NULL); + jtag_add_dr_scan(3, fields, -1); if ((retval = jtag_execute_queue()) != ERROR_OK) { - ERROR("JTAG error while reading DCSR"); - exit(-1); + LOG_ERROR("JTAG error while reading DCSR"); + return retval; } xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0; @@ -313,13 +298,19 @@ int xscale_read_dcsr(target_t *target) jtag_add_end_state(TAP_RTI); - jtag_add_dr_scan(3, fields, -1, NULL); + jtag_add_dr_scan(3, fields, -1); - return ERROR_OK; + /* DANGER!!! this must be here. It will make sure that the arguments + * to jtag_set_check_value() does not go out of scope! */ + return jtag_execute_queue(); } int xscale_receive(target_t *target, u32 *buffer, int num_words) { + if (num_words==0) + return ERROR_INVALID_ARGUMENTS; + + int retval=ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -336,7 +327,6 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) int words_scheduled = 0; int i; - int retval; path[0] = TAP_SDS; path[1] = TAP_CD; @@ -346,7 +336,7 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) fields[0].num_bits = 3; fields[0].out_value = NULL; fields[0].out_mask = NULL; - /* fields[0].in_value = field0; */ + fields[0].in_value = NULL; jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL); fields[1].device = xscale->jtag_info.chain_pos; @@ -358,8 +348,8 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) fields[1].in_handler_priv = NULL; fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; - - + + fields[2].device = xscale->jtag_info.chain_pos; fields[2].num_bits = 1; @@ -370,9 +360,10 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) jtag_add_end_state(TAP_RTI); xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgtx); - jtag_add_runtest(1, -1); + jtag_add_runtest(1, -1); /* ensures that we're in the TAP_RTI state as the above could be a no-op */ /* repeat until all words have been collected */ + int attempts=0; while (words_done < num_words) { /* schedule reads */ @@ -384,14 +375,14 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) fields[1].in_handler_priv = (u8*)&field1[i]; jtag_add_pathmove(3, path); - jtag_add_dr_scan(3, fields, TAP_RTI, NULL); + jtag_add_dr_scan(3, fields, TAP_RTI); words_scheduled++; } if ((retval = jtag_execute_queue()) != ERROR_OK) { - ERROR("JTAG error while receiving data from debug handler"); - exit(-1); + LOG_ERROR("JTAG error while receiving data from debug handler"); + break; } /* examine results */ @@ -409,6 +400,16 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) words_scheduled--; } } + if (words_scheduled==0) + { + if (attempts++==1000) + { + LOG_ERROR("Failed to receiving data from debug handler after 1000 attempts"); + retval=ERROR_TARGET_TIMEOUT; + break; + } + } + words_done += words_scheduled; } @@ -417,7 +418,7 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) free(field1); - return ERROR_OK; + return retval; } int xscale_read_tx(target_t *target, int consume) @@ -425,6 +426,7 @@ int xscale_read_tx(target_t *target, int consume) armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; enum tap_state path[3]; + enum tap_state noconsume_path[6]; int retval; struct timeval timeout, now; @@ -444,6 +446,13 @@ int xscale_read_tx(target_t *target, int consume) path[1] = TAP_CD; path[2] = TAP_SD; + noconsume_path[0] = TAP_SDS; + noconsume_path[1] = TAP_CD; + noconsume_path[2] = TAP_E1D; + noconsume_path[3] = TAP_PD; + noconsume_path[4] = TAP_E2D; + noconsume_path[5] = TAP_SD; + fields[0].device = xscale->jtag_info.chain_pos; fields[0].num_bits = 3; fields[0].out_value = NULL; @@ -460,8 +469,8 @@ int xscale_read_tx(target_t *target, int consume) fields[1].in_handler_priv = NULL; fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; - - + + fields[2].device = xscale->jtag_info.chain_pos; fields[2].num_bits = 1; @@ -471,34 +480,47 @@ int xscale_read_tx(target_t *target, int consume) jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL); gettimeofday(&timeout, NULL); - timeval_add_time(&timeout, 5, 0); + timeval_add_time(&timeout, 1, 0); - do + for (;;) { - /* if we want to consume the register content (i.e. clear TX_READY), - * we have to go straight from Capture-DR to Shift-DR - * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR - */ - if (consume) - jtag_add_pathmove(3, path); - else - jtag_add_statemove(TAP_PD); - - jtag_add_dr_scan(3, fields, TAP_RTI, NULL); - - if ((retval = jtag_execute_queue()) != ERROR_OK) - { - ERROR("JTAG error while reading TX"); - exit(-1); - } - - gettimeofday(&now, NULL); - if ((now.tv_sec > timeout.tv_sec) && (now.tv_usec > timeout.tv_usec)) + int i; + for (i=0; i<100; i++) { - ERROR("time out reading TX register"); - return ERROR_TARGET_TIMEOUT; + /* if we want to consume the register content (i.e. clear TX_READY), + * we have to go straight from Capture-DR to Shift-DR + * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR + */ + if (consume) + jtag_add_pathmove(3, path); + else + { + jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path); + } + + jtag_add_dr_scan(3, fields, TAP_RTI); + + if ((retval = jtag_execute_queue()) != ERROR_OK) + { + LOG_ERROR("JTAG error while reading TX"); + return ERROR_TARGET_TIMEOUT; + } + + gettimeofday(&now, NULL); + if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec))) + { + LOG_ERROR("time out reading TX register"); + return ERROR_TARGET_TIMEOUT; + } + if (!((!(field0_in & 1)) && consume)) + { + goto done; + } } - } while ((!(field0_in & 1)) && consume); + LOG_DEBUG("waiting 10ms"); + usleep(10*1000); /* avoid flooding the logs */ + } + done: if (!(field0_in & 1)) return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; @@ -543,8 +565,8 @@ int xscale_write_rx(target_t *target) fields[1].in_handler_priv = NULL; fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; - - + + fields[2].device = xscale->jtag_info.chain_pos; fields[2].num_bits = 1; @@ -554,36 +576,45 @@ int xscale_write_rx(target_t *target) jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL); gettimeofday(&timeout, NULL); - timeval_add_time(&timeout, 5, 0); + timeval_add_time(&timeout, 1, 0); /* poll until rx_read is low */ - do + LOG_DEBUG("polling RX"); + for (;;) { - DEBUG("polling RX"); - jtag_add_dr_scan(3, fields, TAP_RTI, NULL); - - if ((retval = jtag_execute_queue()) != ERROR_OK) - { - ERROR("JTAG error while writing RX"); - exit(-1); - } - - gettimeofday(&now, NULL); - if ((now.tv_sec > timeout.tv_sec) && (now.tv_usec > timeout.tv_usec)) + int i; + for (i=0; i<10; i++) { - ERROR("time out writing RX register"); - return ERROR_TARGET_TIMEOUT; + jtag_add_dr_scan(3, fields, TAP_RTI); + + if ((retval = jtag_execute_queue()) != ERROR_OK) + { + LOG_ERROR("JTAG error while writing RX"); + return retval; + } + + gettimeofday(&now, NULL); + if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec))) + { + LOG_ERROR("time out writing RX register"); + return ERROR_TARGET_TIMEOUT; + } + if (!(field0_in & 1)) + goto done; } - } while (field0_in & 1); - + LOG_DEBUG("waiting 10ms"); + usleep(10*1000); /* wait 10ms to avoid flooding the logs */ + } + done: + /* set rx_valid */ field2 = 0x1; - jtag_add_dr_scan(3, fields, TAP_RTI, NULL); + jtag_add_dr_scan(3, fields, TAP_RTI); if ((retval = jtag_execute_queue()) != ERROR_OK) { - ERROR("JTAG error while writing RX"); - exit(-1); + LOG_ERROR("JTAG error while writing RX"); + return retval; } return ERROR_OK; @@ -594,80 +625,64 @@ int xscale_send(target_t *target, u8 *buffer, int count, int size) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; + u32 t[3]; + int bits[3]; int retval; int done_count = 0; - u8 output[4] = {0, 0, 0, 0}; - - scan_field_t fields[3]; - u8 field0_out = 0x0; - u8 field0_in = 0x0; - u8 field0_check_value = 0x2; - u8 field0_check_mask = 0x6; - u8 field2 = 0x1; - u8 field2_check_value = 0x0; - u8 field2_check_mask = 0x1; - + jtag_add_end_state(TAP_RTI); xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgrx); - fields[0].device = xscale->jtag_info.chain_pos; - fields[0].num_bits = 3; - fields[0].out_value = &field0_out; - fields[0].out_mask = NULL; - fields[0].in_value = &field0_in; - jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL); - - fields[1].device = xscale->jtag_info.chain_pos; - fields[1].num_bits = 32; - fields[1].out_value = output; - fields[1].out_mask = NULL; - fields[1].in_value = NULL; - fields[1].in_handler = NULL; - fields[1].in_handler_priv = NULL; - fields[1].in_check_value = NULL; - fields[1].in_check_mask = NULL; - - - - fields[2].device = xscale->jtag_info.chain_pos; - fields[2].num_bits = 1; - fields[2].out_value = &field2; - fields[2].out_mask = NULL; - fields[2].in_value = NULL; - jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL); - + bits[0]=3; + t[0]=0; + bits[1]=32; + t[2]=1; + bits[2]=1; + int endianness = target->endianness; while (done_count++ < count) { - /* extract sized element from target-endian buffer, and put it - * into little-endian output buffer - */ switch (size) { - case 4: - buf_set_u32(output, 0, 32, target_buffer_get_u32(target, buffer)); - break; - case 2: - buf_set_u32(output, 0, 32, target_buffer_get_u16(target, buffer)); - break; - case 1: - output[0] = *buffer; - break; - default: - ERROR("BUG: size neither 4, 2 nor 1"); - exit(-1); + case 4: + if (endianness == TARGET_LITTLE_ENDIAN) + { + t[1]=le_to_h_u32(buffer); + } else + { + t[1]=be_to_h_u32(buffer); + } + break; + case 2: + if (endianness == TARGET_LITTLE_ENDIAN) + { + t[1]=le_to_h_u16(buffer); + } else + { + t[1]=be_to_h_u16(buffer); + } + break; + case 1: + t[1]=buffer[0]; + break; + default: + LOG_ERROR("BUG: size neither 4, 2 nor 1"); + exit(-1); } - - jtag_add_dr_scan(3, fields, TAP_RTI, NULL); + jtag_add_dr_out(xscale->jtag_info.chain_pos, + 3, + bits, + t, + TAP_RTI); buffer += size; } if ((retval = jtag_execute_queue()) != ERROR_OK) { - ERROR("JTAG error while sending data to debug handler"); - exit(-1); + LOG_ERROR("JTAG error while sending data to debug handler"); + return retval; } return ERROR_OK; @@ -725,8 +740,8 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) fields[1].in_handler_priv = NULL; fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; - - + + fields[2].device = xscale->jtag_info.chain_pos; fields[2].num_bits = 1; @@ -735,12 +750,12 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) fields[2].in_value = NULL; jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL); - jtag_add_dr_scan(3, fields, -1, NULL); + jtag_add_dr_scan(3, fields, -1); if ((retval = jtag_execute_queue()) != ERROR_OK) { - ERROR("JTAG error while writing DCSR"); - exit(-1); + LOG_ERROR("JTAG error while writing DCSR"); + return retval; } xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0; @@ -757,7 +772,7 @@ unsigned int parity (unsigned int v) v ^= v >> 8; v ^= v >> 4; v &= 0xf; - DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1); + LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1); return (0x6996 >> v) & 1; } @@ -771,7 +786,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8]) scan_field_t fields[2]; - DEBUG("loading miniIC at 0x%8.8x", va); + LOG_DEBUG("loading miniIC at 0x%8.8x", va); jtag_add_end_state(TAP_RTI); xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.ldic); /* LDIC */ @@ -807,7 +822,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8]) fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; - jtag_add_dr_scan(2, fields, -1, NULL); + jtag_add_dr_scan(2, fields, -1); fields[0].num_bits = 32; fields[0].out_value = packet; @@ -819,7 +834,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8]) { buf_set_u32(packet, 0, 32, buffer[word]); cmd = parity(*((u32*)packet)); - jtag_add_dr_scan(2, fields, -1, NULL); + jtag_add_dr_scan(2, fields, -1); } jtag_execute_queue(); @@ -865,7 +880,7 @@ int xscale_invalidate_ic_line(target_t *target, u32 va) fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; - jtag_add_dr_scan(2, fields, -1, NULL); + jtag_add_dr_scan(2, fields, -1); return ERROR_OK; } @@ -875,6 +890,7 @@ int xscale_update_vectors(target_t *target) armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; int i; + int retval; u32 low_reset_branch, high_reset_branch; @@ -887,8 +903,12 @@ int xscale_update_vectors(target_t *target) } else { - if (target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]) != ERROR_OK) + retval=target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]); + if (retval == ERROR_TARGET_TIMEOUT) + return retval; + if (retval!=ERROR_OK) { + /* Some of these reads will fail as part of normal execution */ xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0); } } @@ -902,8 +922,12 @@ int xscale_update_vectors(target_t *target) } else { - if (target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]) != ERROR_OK) + retval=target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]); + if (retval == ERROR_TARGET_TIMEOUT) + return retval; + if (retval!=ERROR_OK) { + /* Some of these reads will fail as part of normal execution */ xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0); } } @@ -926,7 +950,7 @@ int xscale_update_vectors(target_t *target) return ERROR_OK; } -int xscale_arch_state(struct target_s *target, char *buf, int buf_size) +int xscale_arch_state(struct target_s *target) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -943,12 +967,11 @@ int xscale_arch_state(struct target_s *target, char *buf, int buf_size) if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { - ERROR("BUG: called for a non-ARMv4/5 target"); + LOG_ERROR("BUG: called for a non-ARMv4/5 target"); exit(-1); } - snprintf(buf, buf_size, - "target halted in %s state due to %s, current mode: %s\n" + LOG_USER("target halted in %s state due to %s, current mode: %s\n" "cpsr: 0x%8.8x pc: 0x%8.8x\n" "MMU: %s, D-Cache: %s, I-Cache: %s" "%s", @@ -965,17 +988,17 @@ int xscale_arch_state(struct target_s *target, char *buf, int buf_size) return ERROR_OK; } -enum target_state xscale_poll(target_t *target) +int xscale_poll(target_t *target) { - int retval; + int retval=ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING)) { + enum target_state previous_state = target->state; if ((retval = xscale_read_tx(target, 0)) == ERROR_OK) { - enum target_state previous_state = target->state; /* there's data to read from the tx register, we entered debug state */ xscale->handler_running = 1; @@ -983,30 +1006,30 @@ enum target_state xscale_poll(target_t *target) target->state = TARGET_HALTED; /* process debug entry, fetching current mode regs */ - if ((retval = xscale_debug_entry(target)) != ERROR_OK) - return retval; - - /* debug_entry could have overwritten target state (i.e. immediate resume) - * don't signal event handlers in that case - */ - if (target->state != TARGET_HALTED) - return target->state; - - /* if target was running, signal that we halted - * otherwise we reentered from debug execution */ - if (previous_state == TARGET_RUNNING) - target_call_event_callbacks(target, TARGET_EVENT_HALTED); - else - target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED); + retval = xscale_debug_entry(target); } else if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE) { - ERROR("error while polling TX register"); - exit(-1); + LOG_USER("error while polling TX register, reset CPU"); + /* here we "lie" so GDB won't get stuck and a reset can be perfomed */ + target->state = TARGET_HALTED; } + + /* debug_entry could have overwritten target state (i.e. immediate resume) + * don't signal event handlers in that case + */ + if (target->state != TARGET_HALTED) + return ERROR_OK; + + /* if target was running, signal that we halted + * otherwise we reentered from debug execution */ + if (previous_state == TARGET_RUNNING) + target_call_event_callbacks(target, TARGET_EVENT_HALTED); + else + target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED); } - return target->state; + return retval; } int xscale_debug_entry(target_t *target) @@ -1014,29 +1037,32 @@ int xscale_debug_entry(target_t *target) armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; u32 pc; - u32 *buffer = malloc(4 * 10); + u32 buffer[10]; int i; + int retval; u32 moe; /* clear external dbg break (will be written on next DCSR read) */ xscale->external_debug_break = 0; - xscale_read_dcsr(target); - + if ((retval=xscale_read_dcsr(target))!=ERROR_OK) + return retval; + /* get r0, pc, r1 to r7 and cpsr */ - xscale_receive(target, buffer, 10); + if ((retval=xscale_receive(target, buffer, 10))!=ERROR_OK) + return retval; /* move r0 from buffer to register cache */ buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, buffer[0]); armv4_5->core_cache->reg_list[15].dirty = 1; armv4_5->core_cache->reg_list[15].valid = 1; - DEBUG("r0: 0x%8.8x", buffer[0]); + LOG_DEBUG("r0: 0x%8.8x", buffer[0]); /* move pc from buffer to register cache */ buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, buffer[1]); armv4_5->core_cache->reg_list[15].dirty = 1; armv4_5->core_cache->reg_list[15].valid = 1; - DEBUG("pc: 0x%8.8x", buffer[1]); + LOG_DEBUG("pc: 0x%8.8x", buffer[1]); /* move data from buffer to register cache */ for (i = 1; i <= 7; i++) @@ -1044,28 +1070,32 @@ int xscale_debug_entry(target_t *target) buf_set_u32(armv4_5->core_cache->reg_list[i].value, 0, 32, buffer[1 + i]); armv4_5->core_cache->reg_list[i].dirty = 1; armv4_5->core_cache->reg_list[i].valid = 1; - DEBUG("r%i: 0x%8.8x", i, buffer[i + 1]); + LOG_DEBUG("r%i: 0x%8.8x", i, buffer[i + 1]); } buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, buffer[9]); armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; - DEBUG("cpsr: 0x%8.8x", buffer[9]); + LOG_DEBUG("cpsr: 0x%8.8x", buffer[9]); armv4_5->core_mode = buffer[9] & 0x1f; if (armv4_5_mode_to_number(armv4_5->core_mode) == -1) { target->state = TARGET_UNKNOWN; - ERROR("cpsr contains invalid mode value - communication failure"); + LOG_ERROR("cpsr contains invalid mode value - communication failure"); return ERROR_TARGET_FAILURE; } - DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]); + LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]); if (buffer[9] & 0x20) armv4_5->core_state = ARMV4_5_STATE_THUMB; else armv4_5->core_state = ARMV4_5_STATE_ARM; + + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + return ERROR_FAIL; + /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */ if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS)) { @@ -1134,7 +1164,7 @@ int xscale_debug_entry(target_t *target) break; case 0x7: /* Reserved */ default: - ERROR("Method of Entry is 'Reserved'"); + LOG_ERROR("Method of Entry is 'Reserved'"); exit(-1); break; } @@ -1188,22 +1218,22 @@ int xscale_halt(target_t *target) armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", target_state_strings[target->state]); if (target->state == TARGET_HALTED) { - WARNING("target was already halted"); - return ERROR_TARGET_ALREADY_HALTED; + LOG_DEBUG("target was already halted"); + return ERROR_OK; } else if (target->state == TARGET_UNKNOWN) { /* this must not happen for a xscale target */ - ERROR("target was in unknown state when halt was requested"); - exit(-1); + LOG_ERROR("target was in unknown state when halt was requested"); + return ERROR_TARGET_INVALID; } else if (target->state == TARGET_RESET) { - DEBUG("target->state == TARGET_RESET"); + LOG_DEBUG("target->state == TARGET_RESET"); } else { @@ -1233,7 +1263,7 @@ int xscale_enable_single_step(struct target_s *target, u32 next_pc) } else { - ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found"); + LOG_ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found"); exit(-1); } } @@ -1265,11 +1295,11 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_ int retval; int i; - DEBUG("-"); + LOG_DEBUG("-"); if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1279,7 +1309,8 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_ } /* update vector tables */ - xscale_update_vectors(target); + if ((retval=xscale_update_vectors(target))!=ERROR_OK) + return retval; /* current = 1: continue on current pc, otherwise continue at
*/ if (!current) @@ -1302,7 +1333,7 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_ u32 next_pc; /* there's a breakpoint at the current PC, we have to step over it */ - DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address); + LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address); xscale_unset_breakpoint(target, breakpoint); /* calculate PC of next instruction */ @@ -1310,10 +1341,10 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_ { u32 current_opcode; target_read_u32(target, current_pc, ¤t_opcode); - ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode); + LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode); } - DEBUG("enable single-step"); + LOG_DEBUG("enable single-step"); xscale_enable_single_step(target, next_pc); /* restore banked registers */ @@ -1331,26 +1362,26 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_ /* send CPSR */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); - DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); + LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); for (i = 7; i >= 0; i--) { /* send register */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); - DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); + LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); } /* send PC */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); - DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); + LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); /* wait for and process debug entry */ xscale_debug_entry(target); - DEBUG("disable single-step"); + LOG_DEBUG("disable single-step"); xscale_disable_single_step(target); - DEBUG("set breakpoint at 0x%8.8x", breakpoint->address); + LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address); xscale_set_breakpoint(target, breakpoint); } } @@ -1374,18 +1405,18 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_ /* send CPSR */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); - DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); + LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); for (i = 7; i >= 0; i--) { /* send register */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); - DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); + LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); } /* send PC */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); - DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); + LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); target->debug_reason = DBG_REASON_NOTHALTED; @@ -1402,7 +1433,7 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_ target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED); } - DEBUG("target resumed"); + LOG_DEBUG("target resumed"); xscale->handler_running = 1; @@ -1421,7 +1452,7 @@ int xscale_step(struct target_s *target, int current, u32 address, int handle_br if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1457,10 +1488,10 @@ int xscale_step(struct target_s *target, int current, u32 address, int handle_br { u32 current_opcode; target_read_u32(target, current_pc, ¤t_opcode); - ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode); + LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode); } - DEBUG("enable single-step"); + LOG_DEBUG("enable single-step"); xscale_enable_single_step(target, next_pc); /* restore banked registers */ @@ -1478,18 +1509,18 @@ int xscale_step(struct target_s *target, int current, u32 address, int handle_br /* send CPSR */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); - DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); + LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); for (i = 7; i >= 0; i--) { /* send register */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); - DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); + LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); } /* send PC */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); - DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); + LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); target_call_event_callbacks(target, TARGET_EVENT_RESUMED); @@ -1499,7 +1530,7 @@ int xscale_step(struct target_s *target, int current, u32 address, int handle_br /* wait for and process debug entry */ xscale_debug_entry(target); - DEBUG("disable single-step"); + LOG_DEBUG("disable single-step"); xscale_disable_single_step(target); target_call_event_callbacks(target, TARGET_EVENT_HALTED); @@ -1509,7 +1540,7 @@ int xscale_step(struct target_s *target, int current, u32 address, int handle_br xscale_set_breakpoint(target, breakpoint); } - DEBUG("target stepped"); + LOG_DEBUG("target stepped"); return ERROR_OK; @@ -1520,7 +1551,7 @@ int xscale_assert_reset(target_t *target) armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", target_state_strings[target->state]); /* select DCSR instruction (set endstate to R-T-I to ensure we don't * end up in T-L-R, which would reset JTAG @@ -1564,7 +1595,7 @@ int xscale_deassert_reset(target_t *target) breakpoint_t *breakpoint = target->breakpoints; - DEBUG("-"); + LOG_DEBUG("-"); xscale->ibcr_available = 2; xscale->ibcr0_used = 0; @@ -1590,7 +1621,7 @@ int xscale_deassert_reset(target_t *target) jtag_add_reset(0, 0); /* wait 300ms; 150 and 100ms were not enough */ - jtag_add_sleep(3000000); + jtag_add_sleep(300*1000); jtag_add_runtest(2030, TAP_RTI); jtag_execute_queue(); @@ -1601,21 +1632,20 @@ int xscale_deassert_reset(target_t *target) xscale_write_dcsr(target, 1, 0); /* Load debug handler */ - if (fileio_open(&debug_handler, PKGLIBDIR "/xscale/debug_handler.bin", FILEIO_READ, FILEIO_BINARY) != ERROR_OK) + if (fileio_open(&debug_handler, "xscale/debug_handler.bin", FILEIO_READ, FILEIO_BINARY) != ERROR_OK) { - ERROR("file open error: %s", debug_handler.error_str); return ERROR_OK; } if ((binary_size = debug_handler.size) % 4) { - ERROR("debug_handler.bin: size not a multiple of 4"); + LOG_ERROR("debug_handler.bin: size not a multiple of 4"); exit(-1); } if (binary_size > 0x800) { - ERROR("debug_handler.bin: larger than 2kb"); + LOG_ERROR("debug_handler.bin: larger than 2kb"); exit(-1); } @@ -1629,7 +1659,7 @@ int xscale_deassert_reset(target_t *target) if ((retval = fileio_read(&debug_handler, 32, buffer, &buf_cnt)) != ERROR_OK) { - ERROR("reading debug handler failed: %s", debug_handler.error_str); + } for (i = 0; i < buf_cnt; i += 4) @@ -1669,7 +1699,7 @@ int xscale_deassert_reset(target_t *target) xscale_write_dcsr(target, 0, 1); target->state = TARGET_RUNNING; - if ((target->reset_mode != RESET_HALT) && (target->reset_mode != RESET_INIT)) + if (!target->reset_halt) { jtag_add_sleep(10000); @@ -1680,6 +1710,8 @@ int xscale_deassert_reset(target_t *target) /* resume the target */ xscale_resume(target, 1, 0x0, 1, 0); } + + fileio_close(&debug_handler); } else { @@ -1696,14 +1728,6 @@ int xscale_soft_reset_halt(struct target_s *target) return ERROR_OK; } -int xscale_prepare_reset_halt(struct target_s *target) -{ - /* nothing to be done for reset_halt on XScale targets - * we always halt after a reset to upload the debug handler - */ - return ERROR_OK; -} - int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode) { @@ -1724,11 +1748,11 @@ int xscale_full_context(target_t *target) int i, j; - DEBUG("-"); + LOG_DEBUG("-"); if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1798,11 +1822,11 @@ int xscale_restore_context(target_t *target) int i, j; - DEBUG("-"); + LOG_DEBUG("-"); if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1867,12 +1891,13 @@ int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count xscale_common_t *xscale = armv4_5->arch_info; u32 *buf32; int i; + int retval; - DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count); + LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count); if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1884,17 +1909,21 @@ int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count return ERROR_TARGET_UNALIGNED_ACCESS; /* send memory read request (command 0x1n, n: access size) */ - xscale_send_u32(target, 0x10 | size); + if ((retval=xscale_send_u32(target, 0x10 | size))!=ERROR_OK) + return retval; /* send base address for read request */ - xscale_send_u32(target, address); + if ((retval=xscale_send_u32(target, address))!=ERROR_OK) + return retval; /* send number of requested data words */ - xscale_send_u32(target, count); + if ((retval=xscale_send_u32(target, count))!=ERROR_OK) + return retval; /* receive data from target (count times 32-bit words in host endianness) */ buf32 = malloc(4 * count); - xscale_receive(target, buf32, count); + if ((retval=xscale_receive(target, buf32, count))!=ERROR_OK) + return retval; /* extract data from host-endian buffer into byte stream */ for (i = 0; i < count; i++) @@ -1913,7 +1942,7 @@ int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count *buffer++ = buf32[i] & 0xff; break; default: - ERROR("should never get here"); + LOG_ERROR("should never get here"); exit(-1); } } @@ -1921,11 +1950,13 @@ int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count free(buf32); /* examine DCSR, to see if Sticky Abort (SA) got set */ - xscale_read_dcsr(target); + if ((retval=xscale_read_dcsr(target))!=ERROR_OK) + return retval; if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1) { /* clear SA bit */ - xscale_send_u32(target, 0x60); + if ((retval=xscale_send_u32(target, 0x60))!=ERROR_OK) + return retval; return ERROR_TARGET_DATA_ABORT; } @@ -1937,12 +1968,13 @@ int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 coun { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; + int retval; - DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count); + LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count); if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1954,13 +1986,16 @@ int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 coun return ERROR_TARGET_UNALIGNED_ACCESS; /* send memory write request (command 0x2n, n: access size) */ - xscale_send_u32(target, 0x20 | size); + if ((retval=xscale_send_u32(target, 0x20 | size))!=ERROR_OK) + return retval; /* send base address for read request */ - xscale_send_u32(target, address); + if ((retval=xscale_send_u32(target, address))!=ERROR_OK) + return retval; /* send number of requested data words to be written*/ - xscale_send_u32(target, count); + if ((retval=xscale_send_u32(target, count))!=ERROR_OK) + return retval; /* extract data from host-endian buffer into byte stream */ #if 0 @@ -1984,19 +2019,22 @@ int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 coun buffer += 1; break; default: - ERROR("should never get here"); + LOG_ERROR("should never get here"); exit(-1); } } #endif - xscale_send(target, buffer, count, size); + if ((retval=xscale_send(target, buffer, count, size))!=ERROR_OK) + return retval; /* examine DCSR, to see if Sticky Abort (SA) got set */ - xscale_read_dcsr(target); + if ((retval=xscale_read_dcsr(target))!=ERROR_OK) + return retval; if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1) { /* clear SA bit */ - xscale_send_u32(target, 0x60); + if ((retval=xscale_send_u32(target, 0x60))!=ERROR_OK) + return retval; return ERROR_TARGET_DATA_ABORT; } @@ -2006,14 +2044,7 @@ int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 coun int xscale_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer) { - xscale_write_memory(target, address, 4, count, buffer); - - return ERROR_OK; -} - -int xscale_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum) -{ - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + return xscale_write_memory(target, address, 4, count, buffer); } u32 xscale_get_ttb(target_t *target) @@ -2100,7 +2131,7 @@ int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2109,7 +2140,7 @@ int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (breakpoint->set) { - WARNING("breakpoint already set"); + LOG_WARNING("breakpoint already set"); return ERROR_OK; } @@ -2130,7 +2161,7 @@ int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) } else { - ERROR("BUG: no hardware comparator available"); + LOG_ERROR("BUG: no hardware comparator available"); return ERROR_OK; } } @@ -2164,19 +2195,19 @@ int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } if (xscale->force_hw_bkpts) { - DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address); + LOG_DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address); breakpoint->type = BKPT_HARD; } if ((breakpoint->type == BKPT_HARD) && (xscale->ibcr_available < 1)) { - INFO("no breakpoint unit available for hardware breakpoint"); + LOG_INFO("no breakpoint unit available for hardware breakpoint"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } else @@ -2186,7 +2217,7 @@ int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if ((breakpoint->length != 2) && (breakpoint->length != 4)) { - INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported"); + LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -2200,13 +2231,13 @@ int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } if (!breakpoint->set) { - WARNING("breakpoint not set"); + LOG_WARNING("breakpoint not set"); return ERROR_OK; } @@ -2248,7 +2279,7 @@ int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2267,13 +2298,13 @@ int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - u8 enable; + u8 enable=0; reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON]; u32 dbcon_value = buf_get_u32(dbcon->value, 0, 32); if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2291,7 +2322,7 @@ int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) enable = 0x1; break; default: - ERROR("BUG: watchpoint->rw neither read, write nor access"); + LOG_ERROR("BUG: watchpoint->rw neither read, write nor access"); } if (!xscale->dbr0_used) @@ -2312,7 +2343,7 @@ int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) } else { - ERROR("BUG: no hardware comparator available"); + LOG_ERROR("BUG: no hardware comparator available"); return ERROR_OK; } @@ -2326,7 +2357,7 @@ int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2354,13 +2385,13 @@ int xscale_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } if (!watchpoint->set) { - WARNING("breakpoint not set"); + LOG_WARNING("breakpoint not set"); return ERROR_OK; } @@ -2388,7 +2419,7 @@ int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2566,7 +2597,7 @@ int xscale_read_trace(target_t *target) if (target->state != TARGET_HALTED) { - WARNING("target must be stopped to read trace data"); + LOG_WARNING("target must be stopped to read trace data"); return ERROR_TARGET_NOT_HALTED; } @@ -2601,7 +2632,7 @@ int xscale_read_trace(target_t *target) if (j == 256) { - DEBUG("no trace data collected"); + LOG_DEBUG("no trace data collected"); return ERROR_XSCALE_NO_TRACE_DATA; } @@ -2666,7 +2697,7 @@ int xscale_read_instruction(target_t *target, arm_instruction_t *instruction) xscale->trace.current_pc - xscale->trace.image->sections[section].base_address, 4, buf, &size_read)) != ERROR_OK) { - ERROR("error while reading instruction: %i", retval); + LOG_ERROR("error while reading instruction: %i", retval); return ERROR_TRACE_INSTRUCTION_UNAVAILABLE; } opcode = target_buffer_get_u32(target, buf); @@ -2679,7 +2710,7 @@ int xscale_read_instruction(target_t *target, arm_instruction_t *instruction) xscale->trace.current_pc - xscale->trace.image->sections[section].base_address, 2, buf, &size_read)) != ERROR_OK) { - ERROR("error while reading instruction: %i", retval); + LOG_ERROR("error while reading instruction: %i", retval); return ERROR_TRACE_INSTRUCTION_UNAVAILABLE; } opcode = target_buffer_get_u16(target, buf); @@ -2687,7 +2718,7 @@ int xscale_read_instruction(target_t *target, arm_instruction_t *instruction) } else { - ERROR("BUG: unknown core state encountered"); + LOG_ERROR("BUG: unknown core state encountered"); exit(-1); } @@ -2770,7 +2801,7 @@ int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx) next_pc_ok = 1; if (((chkpt == 0) && (next_pc != trace_data->chkpt0)) || ((chkpt == 1) && (next_pc != trace_data->chkpt1))) - WARNING("checkpointed indirect branch target address doesn't match checkpoint"); + LOG_WARNING("checkpointed indirect branch target address doesn't match checkpoint"); } /* explicit fall-through */ case 12: /* Checkpointed Direct Branch */ @@ -2789,7 +2820,7 @@ int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx) } else { - WARNING("more than two checkpointed branches encountered"); + LOG_WARNING("more than two checkpointed branches encountered"); } break; case 15: /* Roll-over */ @@ -2797,7 +2828,7 @@ int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx) continue; default: /* Reserved */ command_print(cmd_ctx, "--- reserved trace message ---"); - ERROR("BUG: trace message %i is reserved", (trace_data->entries[i].data & 0xf0) >> 4); + LOG_ERROR("BUG: trace message %i is reserved", (trace_data->entries[i].data & 0xf0) >> 4); return ERROR_OK; } @@ -2945,18 +2976,6 @@ void xscale_build_reg_cache(target_t *target) int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *target) { - if (startup_mode != DAEMON_RESET) - { - ERROR("XScale target requires a reset"); - ERROR("Reset target to enable debug"); - } - - /* assert TRST once during startup */ - jtag_add_reset(1, 0); - jtag_add_sleep(5000); - jtag_add_reset(0, 0); - jtag_execute_queue(); - return ERROR_OK; } @@ -2983,7 +3002,6 @@ int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, int chain_p /* prepare JTAG information for the new target */ xscale->jtag_info.chain_pos = chain_pos; - jtag_register_event_callback(xscale_jtag_callback, target); xscale->jtag_info.dbgrx = 0x02; xscale->jtag_info.dbgtx = 0x10; @@ -3073,7 +3091,7 @@ int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, int chain_p xscale->armv4_5_mmu.enable_mmu_caches = xscale_enable_mmu_caches; xscale->armv4_5_mmu.has_tiny_pages = 1; xscale->armv4_5_mmu.mmu_enabled = 0; - + return ERROR_OK; } @@ -3083,11 +3101,12 @@ int xscale_target_command(struct command_context_s *cmd_ctx, char *cmd, char **a int chain_pos; char *variant = NULL; xscale_common_t *xscale = malloc(sizeof(xscale_common_t)); + memset(xscale, 0, sizeof(*xscale)); if (argc < 5) { - ERROR("'target xscale' requires four arguments: "); - exit(-1); + LOG_ERROR("'target xscale' requires four arguments: "); + return ERROR_OK; } chain_pos = strtoul(args[3], NULL, 0); @@ -3110,19 +3129,18 @@ int xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, char if (argc < 2) { - ERROR("'xscale debug_handler
' command takes two required operands"); + LOG_ERROR("'xscale debug_handler
' command takes two required operands"); return ERROR_OK; } if ((target = get_target_by_num(strtoul(args[0], NULL, 0))) == NULL) { - ERROR("no target '%s' configured", args[0]); + LOG_ERROR("no target '%s' configured", args[0]); return ERROR_OK; } if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) { - command_print(cmd_ctx, "target isn't an ARM920t target"); return ERROR_OK; } @@ -3135,7 +3153,7 @@ int xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, char } else { - ERROR("xscale debug_handler
must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800"); + LOG_ERROR("xscale debug_handler
must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800"); } return ERROR_OK; @@ -3151,19 +3169,18 @@ int xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx, if (argc < 2) { - ERROR("'xscale cache_clean_address
' command takes two required operands"); + LOG_ERROR("'xscale cache_clean_address
' command takes two required operands"); return ERROR_OK; } if ((target = get_target_by_num(strtoul(args[0], NULL, 0))) == NULL) { - ERROR("no target '%s' configured", args[0]); + LOG_ERROR("no target '%s' configured", args[0]); return ERROR_OK; } if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) { - command_print(cmd_ctx, "target isn't an XScale target"); return ERROR_OK; } @@ -3171,7 +3188,7 @@ int xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx, if (cache_clean_address & 0xffff) { - ERROR("xscale cache_clean_address
must be 64kb aligned"); + LOG_ERROR("xscale cache_clean_address
must be 64kb aligned"); } else { @@ -3189,34 +3206,51 @@ int xscale_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cm if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) { - command_print(cmd_ctx, "target isn't an XScale target"); return ERROR_OK; } return armv4_5_handle_cache_info_command(cmd_ctx, &xscale->armv4_5_mmu.armv4_5_cache); } -int xscale_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) +static int xscale_virt2phys(struct target_s *target, u32 virtual, u32 *physical) { - target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; xscale_common_t *xscale; - - if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) + int retval; + int type; + u32 cb; + int domain; + u32 ap; + + + if ((retval = xscale_get_arch_pointers(target, &armv4_5, &xscale)) != ERROR_OK) { - command_print(cmd_ctx, "target isn't an XScale target"); - return ERROR_OK; + return retval; + } + u32 ret = armv4_5_mmu_translate_va(target, &xscale->armv4_5_mmu, virtual, &type, &cb, &domain, &ap); + if (type == -1) + { + return ret; } + *physical = ret; + return ERROR_OK; +} +static int xscale_mmu(struct target_s *target, int *enabled) +{ + armv4_5_common_t *armv4_5 = target->arch_info; + xscale_common_t *xscale = armv4_5->arch_info; + if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); - return ERROR_OK; + LOG_ERROR("Target not halted"); + return ERROR_TARGET_INVALID; } - - return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &xscale->armv4_5_mmu); + *enabled = xscale->armv4_5_mmu.mmu_enabled; + return ERROR_OK; } + int xscale_handle_mmu_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); @@ -3225,7 +3259,6 @@ int xscale_handle_mmu_command(command_context_t *cmd_ctx, char *cmd, char **args if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) { - command_print(cmd_ctx, "target isn't an XScale target"); return ERROR_OK; } @@ -3263,7 +3296,6 @@ int xscale_handle_idcache_command(command_context_t *cmd_ctx, char *cmd, char ** if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) { - command_print(cmd_ctx, "target isn't an XScale target"); return ERROR_OK; } @@ -3317,7 +3349,6 @@ int xscale_handle_vector_catch_command(command_context_t *cmd_ctx, char *cmd, ch if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) { - command_print(cmd_ctx, "target isn't an XScale target"); return ERROR_OK; } @@ -3345,7 +3376,6 @@ int xscale_handle_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) { - command_print(cmd_ctx, "target isn't an XScale target"); return ERROR_OK; } @@ -3376,7 +3406,6 @@ int xscale_handle_trace_buffer_command(struct command_context_s *cmd_ctx, char * if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) { - command_print(cmd_ctx, "target isn't an XScale target"); return ERROR_OK; } @@ -3463,7 +3492,6 @@ int xscale_handle_trace_image_command(struct command_context_s *cmd_ctx, char *c if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) { - command_print(cmd_ctx, "target isn't an XScale target"); return ERROR_OK; } @@ -3491,7 +3519,6 @@ int xscale_handle_trace_image_command(struct command_context_s *cmd_ctx, char *c if (image_open(xscale->trace.image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK) { - command_print(cmd_ctx, "image opening error: %s", xscale->trace.image->error_str); free(xscale->trace.image); xscale->trace.image = NULL; return ERROR_OK; @@ -3510,7 +3537,6 @@ int xscale_handle_dump_trace_command(struct command_context_s *cmd_ctx, char *cm if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) { - command_print(cmd_ctx, "target isn't an XScale target"); return ERROR_OK; } @@ -3536,7 +3562,6 @@ int xscale_handle_dump_trace_command(struct command_context_s *cmd_ctx, char *cm if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK) { - command_print(cmd_ctx, "file open error: %s", file.error_str); return ERROR_OK; } @@ -3568,7 +3593,6 @@ int xscale_handle_analyze_trace_buffer_command(struct command_context_s *cmd_ctx if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) { - command_print(cmd_ctx, "target isn't an XScale target"); return ERROR_OK; } @@ -3577,17 +3601,105 @@ int xscale_handle_analyze_trace_buffer_command(struct command_context_s *cmd_ctx return ERROR_OK; } +int xscale_handle_cp15(command_context_t *cmd_ctx, char *cmd, char **args, int argc) +{ + target_t *target = get_current_target(cmd_ctx); + armv4_5_common_t *armv4_5; + xscale_common_t *xscale; + + if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) + { + return ERROR_OK; + } + + if (target->state != TARGET_HALTED) + { + command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); + return ERROR_OK; + } + u32 reg_no = 0; + reg_t *reg = NULL; + if(argc > 0) + { + reg_no = strtoul(args[0], NULL, 0); + /*translate from xscale cp15 register no to openocd register*/ + switch(reg_no) + { + case 0: + reg_no = XSCALE_MAINID; + break; + case 1: + reg_no = XSCALE_CTRL; + break; + case 2: + reg_no = XSCALE_TTB; + break; + case 3: + reg_no = XSCALE_DAC; + break; + case 5: + reg_no = XSCALE_FSR; + break; + case 6: + reg_no = XSCALE_FAR; + break; + case 13: + reg_no = XSCALE_PID; + break; + case 15: + reg_no = XSCALE_CPACCESS; + break; + default: + command_print(cmd_ctx, "invalid register number"); + return ERROR_INVALID_ARGUMENTS; + } + reg = &xscale->reg_cache->reg_list[reg_no]; + + } + if(argc == 1) + { + u32 value; + + /* read cp15 control register */ + xscale_get_reg(reg); + value = buf_get_u32(reg->value, 0, 32); + command_print(cmd_ctx, "%s (/%i): 0x%x", reg->name, reg->size, value); + } + else if(argc == 2) + { + + u32 value = strtoul(args[1], NULL, 0); + + /* send CP write request (command 0x41) */ + xscale_send_u32(target, 0x41); + + /* send CP register number */ + xscale_send_u32(target, reg_no); + + /* send CP register value */ + xscale_send_u32(target, value); + + /* execute cpwait to ensure outstanding operations complete */ + xscale_send_u32(target, 0x53); + } + else + { + command_print(cmd_ctx, "usage: cp15 [register]<, [value]>"); + } + + return ERROR_OK; +} + int xscale_register_commands(struct command_context_s *cmd_ctx) { command_t *xscale_cmd; xscale_cmd = register_command(cmd_ctx, NULL, "xscale", NULL, COMMAND_ANY, "xscale specific commands"); - register_command(cmd_ctx, xscale_cmd, "debug_handler", xscale_handle_debug_handler_command, COMMAND_CONFIG, NULL); + register_command(cmd_ctx, xscale_cmd, "debug_handler", xscale_handle_debug_handler_command, COMMAND_ANY, "'xscale debug_handler
' command takes two required operands"); register_command(cmd_ctx, xscale_cmd, "cache_clean_address", xscale_handle_cache_clean_address_command, COMMAND_ANY, NULL); register_command(cmd_ctx, xscale_cmd, "cache_info", xscale_handle_cache_info_command, COMMAND_EXEC, NULL); - register_command(cmd_ctx, xscale_cmd, "virt2phys", xscale_handle_virt2phys_command, COMMAND_EXEC, NULL); register_command(cmd_ctx, xscale_cmd, "mmu", xscale_handle_mmu_command, COMMAND_EXEC, "['enable'|'disable'] the MMU"); register_command(cmd_ctx, xscale_cmd, "icache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the ICache"); register_command(cmd_ctx, xscale_cmd, "dcache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the DCache"); @@ -3601,6 +3713,8 @@ int xscale_register_commands(struct command_context_s *cmd_ctx) register_command(cmd_ctx, xscale_cmd, "trace_image", xscale_handle_trace_image_command, COMMAND_EXEC, "load image from [base address]"); + register_command(cmd_ctx, xscale_cmd, "cp15", xscale_handle_cp15, COMMAND_EXEC, "access coproc 15 [value]"); + armv4_5_register_commands(cmd_ctx); return ERROR_OK;