X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fxscale.c;h=d8977e2189e77804ea7e1dfa59be7a8559a49ff2;hp=7de1d84401955ccb836cad6974ef58250bee8ff9;hb=aa7c449600d6f6d634f587de6091421a1a877af5;hpb=53d605e12c3765aeedabf2bfe0c5cc338dc95d5a diff --git a/src/target/xscale.c b/src/target/xscale.c index 7de1d84401..d8977e2189 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -2,9 +2,12 @@ * Copyright (C) 2006, 2007 by Dominic Rath * * Dominic.Rath@gmx.de * * * - * Copyright (C) 2007,2008 Øyvind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyvind.harboe@zylin.com * * * + * Copyright (C) 2009 Michael Schwingen * + * michael@schwingen.org * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -24,6 +27,7 @@ #include "config.h" #endif +#include "breakpoints.h" #include "xscale.h" #include "target_type.h" #include "arm7_9_common.h" @@ -32,90 +36,52 @@ #include "time_support.h" #include "image.h" -/* cli handling */ -int xscale_register_commands(struct command_context_s *cmd_ctx); - -/* forward declarations */ -int xscale_target_create(struct target_s *target, Jim_Interp *interp); -int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int xscale_quit(void); - -int xscale_arch_state(struct target_s *target); -int xscale_poll(target_t *target); -int xscale_halt(target_t *target); -int xscale_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution); -int xscale_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints); -int xscale_debug_entry(target_t *target); -int xscale_restore_context(target_t *target); - -int xscale_assert_reset(target_t *target); -int xscale_deassert_reset(target_t *target); -int xscale_soft_reset_halt(struct target_s *target); - -int xscale_set_reg_u32(reg_t *reg, uint32_t value); - -int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode); -int xscale_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value); - -int xscale_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); -int xscale_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); -int xscale_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer); - -int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint); -int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint); -int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint); -int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint); -int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint); -int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint); -void xscale_enable_watchpoints(struct target_s *target); -void xscale_enable_breakpoints(struct target_s *target); -static int xscale_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical); -static int xscale_mmu(struct target_s *target, int *enabled); - -int xscale_read_trace(target_t *target); - -target_type_t xscale_target = -{ - .name = "xscale", - - .poll = xscale_poll, - .arch_state = xscale_arch_state, - .target_request_data = NULL, +/* + * Important XScale documents available as of October 2009 include: + * + * Intel XScale® Core Developer’s Manual, January 2004 + * Order Number: 273473-002 + * This has a chapter detailing debug facilities, and punts some + * details to chip-specific microarchitecture documents. + * + * Hot-Debug for Intel XScale® Core Debug White Paper, May 2005 + * Document Number: 273539-005 + * Less detailed than the developer's manual, but summarizes those + * missing details (for most XScales) and gives LOTS of notes about + * debugger/handler interaction issues. Presents a simpler reset + * and load-handler sequence than the arch doc. (Note, OpenOCD + * doesn't currently support "Hot-Debug" as defined there.) + * + * Chip-specific microarchitecture documents may also be useful. + */ - .halt = xscale_halt, - .resume = xscale_resume, - .step = xscale_step, - - .assert_reset = xscale_assert_reset, - .deassert_reset = xscale_deassert_reset, - .soft_reset_halt = xscale_soft_reset_halt, - - .get_gdb_reg_list = armv4_5_get_gdb_reg_list, - - .read_memory = xscale_read_memory, - .write_memory = xscale_write_memory, - .bulk_write_memory = xscale_bulk_write_memory, - .checksum_memory = arm7_9_checksum_memory, - .blank_check_memory = arm7_9_blank_check_memory, - - .run_algorithm = armv4_5_run_algorithm, - .add_breakpoint = xscale_add_breakpoint, - .remove_breakpoint = xscale_remove_breakpoint, - .add_watchpoint = xscale_add_watchpoint, - .remove_watchpoint = xscale_remove_watchpoint, - - .register_commands = xscale_register_commands, - .target_create = xscale_target_create, - .init_target = xscale_init_target, - .quit = xscale_quit, - - .virt2phys = xscale_virt2phys, - .mmu = xscale_mmu -}; - -char* xscale_reg_list[] = +/* forward declarations */ +static int xscale_resume(struct target *, int current, + uint32_t address, int handle_breakpoints, int debug_execution); +static int xscale_debug_entry(struct target *); +static int xscale_restore_context(struct target *); +static int xscale_get_reg(struct reg *reg); +static int xscale_set_reg(struct reg *reg, uint8_t *buf); +static int xscale_set_breakpoint(struct target *, struct breakpoint *); +static int xscale_set_watchpoint(struct target *, struct watchpoint *); +static int xscale_unset_breakpoint(struct target *, struct breakpoint *); +static int xscale_read_trace(struct target *); + + +/* This XScale "debug handler" is loaded into the processor's + * mini-ICache, which is 2K of code writable only via JTAG. + * + * FIXME the OpenOCD "bin2char" utility currently doesn't handle + * binary files cleanly. It's string oriented, and terminates them + * with a NUL character. Better would be to generate the constants + * and let other code decide names, scoping, and other housekeeping. + */ +static /* unsigned const char xscale_debug_handler[] = ... */ +#include "xscale_debug.h" + +static char *const xscale_reg_list[] = { "XSCALE_MAINID", /* 0 */ "XSCALE_CACHETYPE", @@ -141,7 +107,7 @@ char* xscale_reg_list[] = "XSCALE_TXRXCTRL", }; -xscale_reg_t xscale_reg_arch_info[] = +static const struct xscale_reg xscale_reg_arch_info[] = { {XSCALE_MAINID, NULL}, {XSCALE_CACHETYPE, NULL}, @@ -167,70 +133,57 @@ xscale_reg_t xscale_reg_arch_info[] = {-1, NULL}, /* TXRXCTRL implicit access via JTAG */ }; -int xscale_reg_arch_type = -1; +static int xscale_reg_arch_type = -1; -int xscale_get_reg(reg_t *reg); -int xscale_set_reg(reg_t *reg, uint8_t *buf); - -int xscale_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, xscale_common_t **xscale_p) +/* convenience wrapper to access XScale specific registers */ +static int xscale_set_reg_u32(struct reg *reg, uint32_t value) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; + uint8_t buf[4]; - if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) - { - LOG_ERROR("target isn't an XScale target"); - return -1; - } + buf_set_u32(buf, 0, 32, value); - if (xscale->common_magic != XSCALE_COMMON_MAGIC) - { - LOG_ERROR("target isn't an XScale target"); - return -1; - } + return xscale_set_reg(reg, buf); +} - *armv4_5_p = armv4_5; - *xscale_p = xscale; +static const char xscale_not[] = "target is not an XScale"; +static int xscale_verify_pointer(struct command_context *cmd_ctx, + struct xscale_common *xscale) +{ + if (xscale->common_magic != XSCALE_COMMON_MAGIC) { + command_print(cmd_ctx, xscale_not); + return ERROR_TARGET_INVALID; + } return ERROR_OK; } -int xscale_jtag_set_instr(jtag_tap_t *tap, uint32_t new_instr) +static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr) { - if (tap==NULL) + if (tap == NULL) return ERROR_FAIL; if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) { - scan_field_t field; + struct scan_field field; + uint8_t scratch[4]; + memset(&field, 0, sizeof field); field.tap = tap; field.num_bits = tap->ir_length; - field.out_value = calloc(CEIL(field.num_bits, 8), 1); + field.out_value = scratch; buf_set_u32(field.out_value, 0, field.num_bits, new_instr); - uint8_t tmp[4]; - field.in_value = tmp; - jtag_add_ir_scan(1, &field, jtag_get_end_state()); - - /* FIX!!!! isn't this check superfluous? verify_ircapture handles this? */ - jtag_check_value_mask(&field, tap->expected, tap->expected_mask); - - free(field.out_value); } return ERROR_OK; } -int xscale_read_dcsr(target_t *target) +static int xscale_read_dcsr(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; - + struct xscale_common *xscale = target_to_xscale(target); int retval; - - scan_field_t fields[3]; + struct scan_field fields[3]; uint8_t field0 = 0x0; uint8_t field0_check_value = 0x2; uint8_t field0_check_mask = 0x7; @@ -239,24 +192,24 @@ int xscale_read_dcsr(target_t *target) uint8_t field2_check_mask = 0x1; jtag_set_end_state(TAP_DRPAUSE); - xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr); + xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR); buf_set_u32(&field0, 1, 1, xscale->hold_rst); buf_set_u32(&field0, 2, 1, xscale->external_debug_break); - fields[0].tap = xscale->jtag_info.tap; + memset(&fields, 0, sizeof fields); + + fields[0].tap = target->tap; fields[0].num_bits = 3; fields[0].out_value = &field0; uint8_t tmp; fields[0].in_value = &tmp; - fields[1].tap = xscale->jtag_info.tap; + fields[1].tap = target->tap; fields[1].num_bits = 32; - fields[1].out_value = NULL; fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value; - - fields[2].tap = xscale->jtag_info.tap; + fields[2].tap = target->tap; fields[2].num_bits = 1; fields[2].out_value = &field2; uint8_t tmp2; @@ -264,8 +217,8 @@ int xscale_read_dcsr(target_t *target) jtag_add_dr_scan(3, fields, jtag_get_end_state()); - jtag_check_value_mask(fields+0, &field0_check_value, &field0_check_mask); - jtag_check_value_mask(fields+2, &field2_check_value, &field2_check_mask); + jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask); + jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask); if ((retval = jtag_execute_queue()) != ERROR_OK) { @@ -295,22 +248,18 @@ int xscale_read_dcsr(target_t *target) static void xscale_getbuf(jtag_callback_data_t arg) { - uint8_t *in=(uint8_t *)arg; - *((uint32_t *)in)=buf_get_u32(in, 0, 32); + uint8_t *in = (uint8_t *)arg; + *((uint32_t *)in) = buf_get_u32(in, 0, 32); } -int xscale_receive(target_t *target, uint32_t *buffer, int num_words) +static int xscale_receive(struct target *target, uint32_t *buffer, int num_words) { - if (num_words==0) + if (num_words == 0) return ERROR_INVALID_ARGUMENTS; - int retval=ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; - + int retval = ERROR_OK; tap_state_t path[3]; - scan_field_t fields[3]; - + struct scan_field fields[3]; uint8_t *field0 = malloc(num_words * 1); uint8_t field0_check_value = 0x2; uint8_t field0_check_mask = 0x6; @@ -319,39 +268,33 @@ int xscale_receive(target_t *target, uint32_t *buffer, int num_words) uint8_t field2_check_mask = 0x1; int words_done = 0; int words_scheduled = 0; - int i; path[0] = TAP_DRSELECT; path[1] = TAP_DRCAPTURE; path[2] = TAP_DRSHIFT; - fields[0].tap = xscale->jtag_info.tap; + memset(&fields, 0, sizeof fields); + + fields[0].tap = target->tap; fields[0].num_bits = 3; - fields[0].out_value = NULL; - fields[0].in_value = NULL; fields[0].check_value = &field0_check_value; fields[0].check_mask = &field0_check_mask; - fields[1].tap = xscale->jtag_info.tap; + fields[1].tap = target->tap; fields[1].num_bits = 32; - fields[1].out_value = NULL; - fields[1].check_value = NULL; - fields[1].check_mask = NULL; - fields[2].tap = xscale->jtag_info.tap; + fields[2].tap = target->tap; fields[2].num_bits = 1; - fields[2].out_value = NULL; - fields[2].in_value = NULL; fields[2].check_value = &field2_check_value; fields[2].check_mask = &field2_check_mask; jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx); + xscale_jtag_set_instr(target->tap, XSCALE_DBGTX); jtag_add_runtest(1, jtag_get_end_state()); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */ /* repeat until all words have been collected */ - int attempts=0; + int attempts = 0; while (words_done < num_words) { /* schedule reads */ @@ -362,11 +305,11 @@ int xscale_receive(target_t *target, uint32_t *buffer, int num_words) jtag_add_pathmove(3, path); - fields[1].in_value = (uint8_t *)(field1+i); + fields[1].in_value = (uint8_t *)(field1 + i); jtag_add_dr_scan_check(3, fields, jtag_set_end_state(TAP_IDLE)); - jtag_add_callback(xscale_getbuf, (jtag_callback_data_t)(field1+i)); + jtag_add_callback(xscale_getbuf, (jtag_callback_data_t)(field1 + i)); words_scheduled++; } @@ -386,18 +329,18 @@ int xscale_receive(target_t *target, uint32_t *buffer, int num_words) int j; for (j = i; j < num_words - 1; j++) { - field0[j] = field0[j+1]; - field1[j] = field1[j+1]; + field0[j] = field0[j + 1]; + field1[j] = field1[j + 1]; } words_scheduled--; } } - if (words_scheduled==0) + if (words_scheduled == 0) { if (attempts++==1000) { LOG_ERROR("Failed to receiving data from debug handler after 1000 attempts"); - retval=ERROR_TARGET_TIMEOUT; + retval = ERROR_TARGET_TIMEOUT; break; } } @@ -413,17 +356,14 @@ int xscale_receive(target_t *target, uint32_t *buffer, int num_words) return retval; } -int xscale_read_tx(target_t *target, int consume) +static int xscale_read_tx(struct target *target, int consume) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; + struct xscale_common *xscale = target_to_xscale(target); tap_state_t path[3]; tap_state_t noconsume_path[6]; - int retval; struct timeval timeout, now; - - scan_field_t fields[3]; + struct scan_field fields[3]; uint8_t field0_in = 0x0; uint8_t field0_check_value = 0x2; uint8_t field0_check_mask = 0x6; @@ -432,7 +372,7 @@ int xscale_read_tx(target_t *target, int consume) jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx); + xscale_jtag_set_instr(target->tap, XSCALE_DBGTX); path[0] = TAP_DRSELECT; path[1] = TAP_DRCAPTURE; @@ -445,20 +385,18 @@ int xscale_read_tx(target_t *target, int consume) noconsume_path[4] = TAP_DREXIT2; noconsume_path[5] = TAP_DRSHIFT; - fields[0].tap = xscale->jtag_info.tap; + memset(&fields, 0, sizeof fields); + + fields[0].tap = target->tap; fields[0].num_bits = 3; - fields[0].out_value = NULL; fields[0].in_value = &field0_in; - fields[1].tap = xscale->jtag_info.tap; + fields[1].tap = target->tap; fields[1].num_bits = 32; - fields[1].out_value = NULL; fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value; - - fields[2].tap = xscale->jtag_info.tap; + fields[2].tap = target->tap; fields[2].num_bits = 1; - fields[2].out_value = NULL; uint8_t tmp; fields[2].in_value = &tmp; @@ -480,8 +418,8 @@ int xscale_read_tx(target_t *target, int consume) jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE)); - jtag_check_value_mask(fields+0, &field0_check_value, &field0_check_mask); - jtag_check_value_mask(fields+2, &field2_check_value, &field2_check_mask); + jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask); + jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask); if ((retval = jtag_execute_queue()) != ERROR_OK) { @@ -499,7 +437,7 @@ int xscale_read_tx(target_t *target, int consume) { goto done; } - if (debug_level>=3) + if (debug_level >= 3) { LOG_DEBUG("waiting 100ms"); alive_sleep(100); /* avoid flooding the logs */ @@ -516,15 +454,12 @@ int xscale_read_tx(target_t *target, int consume) return ERROR_OK; } -int xscale_write_rx(target_t *target) +static int xscale_write_rx(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; - + struct xscale_common *xscale = target_to_xscale(target); int retval; struct timeval timeout, now; - - scan_field_t fields[3]; + struct scan_field fields[3]; uint8_t field0_out = 0x0; uint8_t field0_in = 0x0; uint8_t field0_check_value = 0x2; @@ -535,20 +470,20 @@ int xscale_write_rx(target_t *target) jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx); + xscale_jtag_set_instr(target->tap, XSCALE_DBGRX); + + memset(&fields, 0, sizeof fields); - fields[0].tap = xscale->jtag_info.tap; + fields[0].tap = target->tap; fields[0].num_bits = 3; fields[0].out_value = &field0_out; fields[0].in_value = &field0_in; - fields[1].tap = xscale->jtag_info.tap; + fields[1].tap = target->tap; fields[1].num_bits = 32; fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value; - fields[1].in_value = NULL; - - fields[2].tap = xscale->jtag_info.tap; + fields[2].tap = target->tap; fields[2].num_bits = 1; fields[2].out_value = &field2; uint8_t tmp; @@ -563,8 +498,8 @@ int xscale_write_rx(target_t *target) { jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE)); - jtag_check_value_mask(fields+0, &field0_check_value, &field0_check_mask); - jtag_check_value_mask(fields+2, &field2_check_value, &field2_check_mask); + jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask); + jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask); if ((retval = jtag_execute_queue()) != ERROR_OK) { @@ -580,7 +515,7 @@ int xscale_write_rx(target_t *target) } if (!(field0_in & 1)) goto done; - if (debug_level>=3) + if (debug_level >= 3) { LOG_DEBUG("waiting 100ms"); alive_sleep(100); /* avoid flooding the logs */ @@ -605,20 +540,16 @@ int xscale_write_rx(target_t *target) } /* send count elements of size byte to the debug handler */ -int xscale_send(target_t *target, uint8_t *buffer, int count, int size) +static int xscale_send(struct target *target, uint8_t *buffer, int count, int size) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; uint32_t t[3]; int bits[3]; - int retval; - int done_count = 0; jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx); + xscale_jtag_set_instr(target->tap, XSCALE_DBGRX); bits[0]=3; t[0]=0; @@ -655,7 +586,7 @@ int xscale_send(target_t *target, uint8_t *buffer, int count, int size) LOG_ERROR("BUG: size neither 4, 2 nor 1"); exit(-1); } - jtag_add_dr_out(xscale->jtag_info.tap, + jtag_add_dr_out(target->tap, 3, bits, t, @@ -672,23 +603,19 @@ int xscale_send(target_t *target, uint8_t *buffer, int count, int size) return ERROR_OK; } -int xscale_send_u32(target_t *target, uint32_t value) +static int xscale_send_u32(struct target *target, uint32_t value) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; + struct xscale_common *xscale = target_to_xscale(target); buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value); return xscale_write_rx(target); } -int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) +static int xscale_write_dcsr(struct target *target, int hold_rst, int ext_dbg_brk) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; - + struct xscale_common *xscale = target_to_xscale(target); int retval; - - scan_field_t fields[3]; + struct scan_field fields[3]; uint8_t field0 = 0x0; uint8_t field0_check_value = 0x2; uint8_t field0_check_mask = 0x7; @@ -703,24 +630,24 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) xscale->external_debug_break = ext_dbg_brk; jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr); + xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR); buf_set_u32(&field0, 1, 1, xscale->hold_rst); buf_set_u32(&field0, 2, 1, xscale->external_debug_break); - fields[0].tap = xscale->jtag_info.tap; + memset(&fields, 0, sizeof fields); + + fields[0].tap = target->tap; fields[0].num_bits = 3; fields[0].out_value = &field0; uint8_t tmp; fields[0].in_value = &tmp; - fields[1].tap = xscale->jtag_info.tap; + fields[1].tap = target->tap; fields[1].num_bits = 32; fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value; - fields[1].in_value = NULL; - - fields[2].tap = xscale->jtag_info.tap; + fields[2].tap = target->tap; fields[2].num_bits = 1; fields[2].out_value = &field2; uint8_t tmp2; @@ -728,8 +655,8 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) jtag_add_dr_scan(3, fields, jtag_get_end_state()); - jtag_check_value_mask(fields+0, &field0_check_value, &field0_check_mask); - jtag_check_value_mask(fields+2, &field2_check_value, &field2_check_mask); + jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask); + jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask); if ((retval = jtag_execute_queue()) != ERROR_OK) { @@ -744,65 +671,52 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) } /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */ -unsigned int parity (unsigned int v) +static unsigned int parity (unsigned int v) { - unsigned int ov = v; + // unsigned int ov = v; v ^= v >> 16; v ^= v >> 8; v ^= v >> 4; v &= 0xf; - LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1); + // LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1); return (0x6996 >> v) & 1; } -int xscale_load_ic(target_t *target, int mini, uint32_t va, uint32_t buffer[8]) +static int xscale_load_ic(struct target *target, uint32_t va, uint32_t buffer[8]) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; uint8_t packet[4]; uint8_t cmd; int word; - - scan_field_t fields[2]; + struct scan_field fields[2]; LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32 "", va); + /* LDIC into IR */ jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */ - - /* CMD is b010 for Main IC and b011 for Mini IC */ - if (mini) - buf_set_u32(&cmd, 0, 3, 0x3); - else - buf_set_u32(&cmd, 0, 3, 0x2); + xscale_jtag_set_instr(target->tap, XSCALE_LDIC); - buf_set_u32(&cmd, 3, 3, 0x0); + /* CMD is b011 to load a cacheline into the Mini ICache. + * Loading into the main ICache is deprecated, and unused. + * It's followed by three zero bits, and 27 address bits. + */ + buf_set_u32(&cmd, 0, 6, 0x3); /* virtual address of desired cache line */ buf_set_u32(packet, 0, 27, va >> 5); - fields[0].tap = xscale->jtag_info.tap; + memset(&fields, 0, sizeof fields); + + fields[0].tap = target->tap; fields[0].num_bits = 6; fields[0].out_value = &cmd; - fields[0].in_value = NULL; - - - - - - fields[1].tap = xscale->jtag_info.tap; + fields[1].tap = target->tap; fields[1].num_bits = 27; fields[1].out_value = packet; - fields[1].in_value = NULL; - - - - - jtag_add_dr_scan(2, fields, jtag_get_end_state()); + /* rest of packet is a cacheline: 8 instructions, with parity */ fields[0].num_bits = 32; fields[0].out_value = packet; @@ -820,22 +734,17 @@ int xscale_load_ic(target_t *target, int mini, uint32_t va, uint32_t buffer[8]) jtag_add_dr_scan(2, fields, jtag_get_end_state()); } - jtag_execute_queue(); - - return ERROR_OK; + return jtag_execute_queue(); } -int xscale_invalidate_ic_line(target_t *target, uint32_t va) +static int xscale_invalidate_ic_line(struct target *target, uint32_t va) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; uint8_t packet[4]; uint8_t cmd; - - scan_field_t fields[2]; + struct scan_field fields[2]; jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */ + xscale_jtag_set_instr(target->tap, XSCALE_LDIC); /* CMD for invalidate IC line b000, bits [6:4] b000 */ buf_set_u32(&cmd, 0, 6, 0x0); @@ -843,35 +752,24 @@ int xscale_invalidate_ic_line(target_t *target, uint32_t va) /* virtual address of desired cache line */ buf_set_u32(packet, 0, 27, va >> 5); - fields[0].tap = xscale->jtag_info.tap; + memset(&fields, 0, sizeof fields); + + fields[0].tap = target->tap; fields[0].num_bits = 6; fields[0].out_value = &cmd; - fields[0].in_value = NULL; - - - - - - fields[1].tap = xscale->jtag_info.tap; + fields[1].tap = target->tap; fields[1].num_bits = 27; fields[1].out_value = packet; - fields[1].in_value = NULL; - - - - - jtag_add_dr_scan(2, fields, jtag_get_end_state()); return ERROR_OK; } -int xscale_update_vectors(target_t *target) +static int xscale_update_vectors(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; + struct xscale_common *xscale = target_to_xscale(target); int i; int retval; @@ -886,7 +784,7 @@ int xscale_update_vectors(target_t *target) } else { - retval=target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]); + retval = target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]); if (retval == ERROR_TARGET_TIMEOUT) return retval; if (retval != ERROR_OK) @@ -905,7 +803,7 @@ int xscale_update_vectors(target_t *target) } else { - retval=target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]); + retval = target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]); if (retval == ERROR_TARGET_TIMEOUT) return retval; if (retval != ERROR_OK) @@ -927,23 +825,23 @@ int xscale_update_vectors(target_t *target) xscale_invalidate_ic_line(target, 0x0); xscale_invalidate_ic_line(target, 0xffff0000); - xscale_load_ic(target, 1, 0x0, xscale->low_vectors); - xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors); + xscale_load_ic(target, 0x0, xscale->low_vectors); + xscale_load_ic(target, 0xffff0000, xscale->high_vectors); return ERROR_OK; } -int xscale_arch_state(struct target_s *target) +static int xscale_arch_state(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; + struct xscale_common *xscale = target_to_xscale(target); + struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common; - char *state[] = + static const char *state[] = { "disabled", "enabled" }; - char *arch_dbg_reason[] = + static const char *arch_dbg_reason[] = { "", "\n(processor reset)", "\n(trace buffer full)" }; @@ -959,7 +857,7 @@ int xscale_arch_state(struct target_s *target) "MMU: %s, D-Cache: %s, I-Cache: %s" "%s", armv4_5_state_strings[armv4_5->core_state], - Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name , + Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name , armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), @@ -971,11 +869,9 @@ int xscale_arch_state(struct target_s *target) return ERROR_OK; } -int xscale_poll(target_t *target) +static int xscale_poll(struct target *target) { - int retval=ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; + int retval = ERROR_OK; if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING)) { @@ -984,8 +880,6 @@ int xscale_poll(target_t *target) { /* there's data to read from the tx register, we entered debug state */ - xscale->handler_running = 1; - target->state = TARGET_HALTED; /* process debug entry, fetching current mode regs */ @@ -1015,30 +909,29 @@ int xscale_poll(target_t *target) return retval; } -int xscale_debug_entry(target_t *target) +static int xscale_debug_entry(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; + struct xscale_common *xscale = target_to_xscale(target); + struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common; uint32_t pc; uint32_t buffer[10]; int i; int retval; - uint32_t moe; /* clear external dbg break (will be written on next DCSR read) */ xscale->external_debug_break = 0; - if ((retval=xscale_read_dcsr(target)) != ERROR_OK) + if ((retval = xscale_read_dcsr(target)) != ERROR_OK) return retval; /* get r0, pc, r1 to r7 and cpsr */ - if ((retval=xscale_receive(target, buffer, 10)) != ERROR_OK) + if ((retval = xscale_receive(target, buffer, 10)) != ERROR_OK) return retval; /* move r0 from buffer to register cache */ buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, buffer[0]); - armv4_5->core_cache->reg_list[15].dirty = 1; - armv4_5->core_cache->reg_list[15].valid = 1; + armv4_5->core_cache->reg_list[0].dirty = 1; + armv4_5->core_cache->reg_list[0].valid = 1; LOG_DEBUG("r0: 0x%8.8" PRIx32 "", buffer[0]); /* move pc from buffer to register cache */ @@ -1145,7 +1038,7 @@ int xscale_debug_entry(target_t *target) xscale->arch_debug_reason = XSCALE_DBG_REASON_TB_FULL; pc -= 4; break; - case 0x7: /* Reserved */ + case 0x7: /* Reserved (may flag Hot-Debug support) */ default: LOG_ERROR("Method of Entry is 'Reserved'"); exit(-1); @@ -1196,13 +1089,12 @@ int xscale_debug_entry(target_t *target) return ERROR_OK; } -int xscale_halt(target_t *target) +static int xscale_halt(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; + struct xscale_common *xscale = target_to_xscale(target); LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); + target_state_name(target)); if (target->state == TARGET_HALTED) { @@ -1231,16 +1123,15 @@ int xscale_halt(target_t *target) return ERROR_OK; } -int xscale_enable_single_step(struct target_s *target, uint32_t next_pc) +static int xscale_enable_single_step(struct target *target, uint32_t next_pc) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale= armv4_5->arch_info; - reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0]; + struct xscale_common *xscale = target_to_xscale(target); + struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0]; int retval; if (xscale->ibcr0_used) { - breakpoint_t *ibcr0_bp = breakpoint_find(target, buf_get_u32(ibcr0->value, 0, 32) & 0xfffffffe); + struct breakpoint *ibcr0_bp = breakpoint_find(target, buf_get_u32(ibcr0->value, 0, 32) & 0xfffffffe); if (ibcr0_bp) { @@ -1253,33 +1144,56 @@ int xscale_enable_single_step(struct target_s *target, uint32_t next_pc) } } - if ((retval=xscale_set_reg_u32(ibcr0, next_pc | 0x1)) != ERROR_OK) + if ((retval = xscale_set_reg_u32(ibcr0, next_pc | 0x1)) != ERROR_OK) return retval; return ERROR_OK; } -int xscale_disable_single_step(struct target_s *target) +static int xscale_disable_single_step(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale= armv4_5->arch_info; - reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0]; + struct xscale_common *xscale = target_to_xscale(target); + struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0]; int retval; - if ((retval=xscale_set_reg_u32(ibcr0, 0x0)) != ERROR_OK) + if ((retval = xscale_set_reg_u32(ibcr0, 0x0)) != ERROR_OK) return retval; return ERROR_OK; } -int xscale_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) +static void xscale_enable_watchpoints(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale= armv4_5->arch_info; - breakpoint_t *breakpoint = target->breakpoints; + struct watchpoint *watchpoint = target->watchpoints; - uint32_t current_pc; + while (watchpoint) + { + if (watchpoint->set == 0) + xscale_set_watchpoint(target, watchpoint); + watchpoint = watchpoint->next; + } +} + +static void xscale_enable_breakpoints(struct target *target) +{ + struct breakpoint *breakpoint = target->breakpoints; + /* set any pending breakpoints */ + while (breakpoint) + { + if (breakpoint->set == 0) + xscale_set_breakpoint(target, breakpoint); + breakpoint = breakpoint->next; + } +} + +static int xscale_resume(struct target *target, int current, + uint32_t address, int handle_breakpoints, int debug_execution) +{ + struct xscale_common *xscale = target_to_xscale(target); + struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common; + struct breakpoint *breakpoint = target->breakpoints; + uint32_t current_pc; int retval; int i; @@ -1297,7 +1211,7 @@ int xscale_resume(struct target_s *target, int current, uint32_t address, int ha } /* update vector tables */ - if ((retval=xscale_update_vectors(target)) != ERROR_OK) + if ((retval = xscale_update_vectors(target)) != ERROR_OK) return retval; /* current = 1: continue on current pc, otherwise continue at
*/ @@ -1423,16 +1337,14 @@ int xscale_resume(struct target_s *target, int current, uint32_t address, int ha LOG_DEBUG("target resumed"); - xscale->handler_running = 1; - return ERROR_OK; } -static int xscale_step_inner(struct target_s *target, int current, uint32_t address, int handle_breakpoints) +static int xscale_step_inner(struct target *target, int current, + uint32_t address, int handle_breakpoints) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; - + struct xscale_common *xscale = target_to_xscale(target); + struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common; uint32_t next_pc; int retval; int i; @@ -1451,56 +1363,56 @@ static int xscale_step_inner(struct target_s *target, int current, uint32_t addr } LOG_DEBUG("enable single-step"); - if ((retval=xscale_enable_single_step(target, next_pc)) != ERROR_OK) + if ((retval = xscale_enable_single_step(target, next_pc)) != ERROR_OK) return retval; /* restore banked registers */ - if ((retval=xscale_restore_context(target)) != ERROR_OK) + if ((retval = xscale_restore_context(target)) != ERROR_OK) return retval; /* send resume request (command 0x30 or 0x31) * clean the trace buffer if it is to be enabled (0x62) */ if (xscale->trace.buffer_enabled) { - if ((retval=xscale_send_u32(target, 0x62)) != ERROR_OK) + if ((retval = xscale_send_u32(target, 0x62)) != ERROR_OK) return retval; - if ((retval=xscale_send_u32(target, 0x31)) != ERROR_OK) + if ((retval = xscale_send_u32(target, 0x31)) != ERROR_OK) return retval; } else - if ((retval=xscale_send_u32(target, 0x30)) != ERROR_OK) + if ((retval = xscale_send_u32(target, 0x30)) != ERROR_OK) return retval; /* send CPSR */ - if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32))) != ERROR_OK) + if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32))) != ERROR_OK) return retval; LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); for (i = 7; i >= 0; i--) { /* send register */ - if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32))) != ERROR_OK) + if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32))) != ERROR_OK) return retval; LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); } /* send PC */ - if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))) != ERROR_OK) + if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))) != ERROR_OK) return retval; LOG_DEBUG("writing PC with value 0x%8.8" PRIx32, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); target_call_event_callbacks(target, TARGET_EVENT_RESUMED); /* registers are now invalid */ - if ((retval=armv4_5_invalidate_core_regs(target)) != ERROR_OK) + if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK) return retval; /* wait for and process debug entry */ - if ((retval=xscale_debug_entry(target)) != ERROR_OK) + if ((retval = xscale_debug_entry(target)) != ERROR_OK) return retval; LOG_DEBUG("disable single-step"); - if ((retval=xscale_disable_single_step(target)) != ERROR_OK) + if ((retval = xscale_disable_single_step(target)) != ERROR_OK) return retval; target_call_event_callbacks(target, TARGET_EVENT_HALTED); @@ -1508,10 +1420,11 @@ static int xscale_step_inner(struct target_s *target, int current, uint32_t addr return ERROR_OK; } -int xscale_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints) +static int xscale_step(struct target *target, int current, + uint32_t address, int handle_breakpoints) { - armv4_5_common_t *armv4_5 = target->arch_info; - breakpoint_t *breakpoint = target->breakpoints; + struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + struct breakpoint *breakpoint = target->breakpoints; uint32_t current_pc; int retval; @@ -1531,7 +1444,7 @@ int xscale_step(struct target_s *target, int current, uint32_t address, int hand /* if we're at the reset vector, we have to simulate the step */ if (current_pc == 0x0) { - if ((retval=arm_simulate_step(target, NULL)) != ERROR_OK) + if ((retval = arm_simulate_step(target, NULL)) != ERROR_OK) return retval; current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); @@ -1545,7 +1458,7 @@ int xscale_step(struct target_s *target, int current, uint32_t address, int hand if (handle_breakpoints) if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)))) { - if ((retval=xscale_unset_breakpoint(target, breakpoint)) != ERROR_OK) + if ((retval = xscale_unset_breakpoint(target, breakpoint)) != ERROR_OK) return retval; } @@ -1562,19 +1475,18 @@ int xscale_step(struct target_s *target, int current, uint32_t address, int hand } -int xscale_assert_reset(target_t *target) +static int xscale_assert_reset(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; + struct xscale_common *xscale = target_to_xscale(target); LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); + target_state_name(target)); /* select DCSR instruction (set endstate to R-T-I to ensure we don't * end up in T-L-R, which would reset JTAG */ jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr); + xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR); /* set Hold reset, Halt mode and Trap Reset */ buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1); @@ -1582,7 +1494,7 @@ int xscale_assert_reset(target_t *target) xscale_write_dcsr(target, 1, 0); /* select BYPASS, because having DCSR selected caused problems on the PXA27x */ - xscale_jtag_set_instr(xscale->jtag_info.tap, 0x7f); + xscale_jtag_set_instr(target->tap, 0x7f); jtag_execute_queue(); /* assert reset */ @@ -1604,20 +1516,10 @@ int xscale_assert_reset(target_t *target) return ERROR_OK; } -int xscale_deassert_reset(target_t *target) +static int xscale_deassert_reset(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; - - fileio_t debug_handler; - uint32_t address; - uint32_t binary_size; - - uint32_t buf_cnt; - uint32_t i; - int retval; - - breakpoint_t *breakpoint = target->breakpoints; + struct xscale_common *xscale = target_to_xscale(target); + struct breakpoint *breakpoint = target->breakpoints; LOG_DEBUG("-"); @@ -1639,8 +1541,23 @@ int xscale_deassert_reset(target_t *target) breakpoint = breakpoint->next; } - if (!xscale->handler_installed) + armv4_5_invalidate_core_regs(target); + + /* FIXME mark hardware watchpoints got unset too. Also, + * at least some of the XScale registers are invalid... + */ + + /* + * REVISIT: *assumes* we had a SRST+TRST reset so the mini-icache + * contents got invalidated. Safer to force that, so writing new + * contents can't ever fail.. + */ { + uint32_t address; + unsigned buf_cnt; + const uint8_t *buffer = xscale_debug_handler; + int retval; + /* release SRST */ jtag_add_reset(0, 0); @@ -1655,36 +1572,22 @@ int xscale_deassert_reset(target_t *target) buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1); xscale_write_dcsr(target, 1, 0); - /* Load debug handler */ - if (fileio_open(&debug_handler, "xscale/debug_handler.bin", FILEIO_READ, FILEIO_BINARY) != ERROR_OK) - { - return ERROR_OK; - } - - if ((binary_size = debug_handler.size) % 4) - { - LOG_ERROR("debug_handler.bin: size not a multiple of 4"); - exit(-1); - } - - if (binary_size > 0x800) - { - LOG_ERROR("debug_handler.bin: larger than 2kb"); - exit(-1); - } - - binary_size = CEIL(binary_size, 32) * 32; - + /* Load the debug handler into the mini-icache. Since + * it's using halt mode (not monitor mode), it runs in + * "Special Debug State" for access to registers, memory, + * coprocessors, trace data, etc. + */ address = xscale->handler_address; - while (binary_size > 0) + for (unsigned binary_size = sizeof xscale_debug_handler - 1; + binary_size > 0; + binary_size -= buf_cnt, buffer += buf_cnt) { uint32_t cache_line[8]; - uint8_t buffer[32]; + unsigned i; - if ((retval = fileio_read(&debug_handler, 32, buffer, &buf_cnt)) != ERROR_OK) - { - - } + buf_cnt = binary_size; + if (buf_cnt > 32) + buf_cnt = 32; for (i = 0; i < buf_cnt; i += 4) { @@ -1692,23 +1595,31 @@ int xscale_deassert_reset(target_t *target) cache_line[i / 4] = le_to_h_u32(&buffer[i]); } - for (; buf_cnt < 32; buf_cnt += 4) + for (; i < 32; i += 4) { - cache_line[buf_cnt / 4] = 0xe1a08008; + cache_line[i / 4] = 0xe1a08008; } /* only load addresses other than the reset vectors */ if ((address % 0x400) != 0x0) { - xscale_load_ic(target, 1, address, cache_line); + retval = xscale_load_ic(target, address, + cache_line); + if (retval != ERROR_OK) + return retval; } address += buf_cnt; - binary_size -= buf_cnt; }; - xscale_load_ic(target, 1, 0x0, xscale->low_vectors); - xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors); + retval = xscale_load_ic(target, 0x0, + xscale->low_vectors); + if (retval != ERROR_OK) + return retval; + retval = xscale_load_ic(target, 0xffff0000, + xscale->high_vectors); + if (retval != ERROR_OK) + return retval; jtag_add_runtest(30, jtag_set_end_state(TAP_IDLE)); @@ -1734,36 +1645,28 @@ int xscale_deassert_reset(target_t *target) /* resume the target */ xscale_resume(target, 1, 0x0, 1, 0); } - - fileio_close(&debug_handler); - } - else - { - jtag_add_reset(0, 0); } return ERROR_OK; } -int xscale_soft_reset_halt(struct target_s *target) +static int xscale_read_core_reg(struct target *target, int num, + enum armv4_5_mode mode) { + LOG_ERROR("not implemented"); return ERROR_OK; } -int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode) +static int xscale_write_core_reg(struct target *target, int num, + enum armv4_5_mode mode, uint32_t value) { + LOG_ERROR("not implemented"); return ERROR_OK; } -int xscale_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value) +static int xscale_full_context(struct target *target) { - - return ERROR_OK; -} - -int xscale_full_context(target_t *target) -{ - armv4_5_common_t *armv4_5 = target->arch_info; + struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); uint32_t *buffer; @@ -1837,14 +1740,12 @@ int xscale_full_context(target_t *target) return ERROR_OK; } -int xscale_restore_context(target_t *target) +static int xscale_restore_context(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; + struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); int i, j; - LOG_DEBUG("-"); - if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); @@ -1906,10 +1807,10 @@ int xscale_restore_context(target_t *target) return ERROR_OK; } -int xscale_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +static int xscale_read_memory(struct target *target, uint32_t address, + uint32_t size, uint32_t count, uint8_t *buffer) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; + struct xscale_common *xscale = target_to_xscale(target); uint32_t *buf32; uint32_t i; int retval; @@ -1930,20 +1831,20 @@ int xscale_read_memory(struct target_s *target, uint32_t address, uint32_t size, return ERROR_TARGET_UNALIGNED_ACCESS; /* send memory read request (command 0x1n, n: access size) */ - if ((retval=xscale_send_u32(target, 0x10 | size)) != ERROR_OK) + if ((retval = xscale_send_u32(target, 0x10 | size)) != ERROR_OK) return retval; /* send base address for read request */ - if ((retval=xscale_send_u32(target, address)) != ERROR_OK) + if ((retval = xscale_send_u32(target, address)) != ERROR_OK) return retval; /* send number of requested data words */ - if ((retval=xscale_send_u32(target, count)) != ERROR_OK) + if ((retval = xscale_send_u32(target, count)) != ERROR_OK) return retval; /* receive data from target (count times 32-bit words in host endianness) */ buf32 = malloc(4 * count); - if ((retval=xscale_receive(target, buf32, count)) != ERROR_OK) + if ((retval = xscale_receive(target, buf32, count)) != ERROR_OK) return retval; /* extract data from host-endian buffer into byte stream */ @@ -1971,12 +1872,12 @@ int xscale_read_memory(struct target_s *target, uint32_t address, uint32_t size, free(buf32); /* examine DCSR, to see if Sticky Abort (SA) got set */ - if ((retval=xscale_read_dcsr(target)) != ERROR_OK) + if ((retval = xscale_read_dcsr(target)) != ERROR_OK) return retval; if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1) { /* clear SA bit */ - if ((retval=xscale_send_u32(target, 0x60)) != ERROR_OK) + if ((retval = xscale_send_u32(target, 0x60)) != ERROR_OK) return retval; return ERROR_TARGET_DATA_ABORT; @@ -1985,10 +1886,10 @@ int xscale_read_memory(struct target_s *target, uint32_t address, uint32_t size, return ERROR_OK; } -int xscale_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +static int xscale_write_memory(struct target *target, uint32_t address, + uint32_t size, uint32_t count, uint8_t *buffer) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; + struct xscale_common *xscale = target_to_xscale(target); int retval; LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32, address, size, count); @@ -2007,15 +1908,15 @@ int xscale_write_memory(struct target_s *target, uint32_t address, uint32_t size return ERROR_TARGET_UNALIGNED_ACCESS; /* send memory write request (command 0x2n, n: access size) */ - if ((retval=xscale_send_u32(target, 0x20 | size)) != ERROR_OK) + if ((retval = xscale_send_u32(target, 0x20 | size)) != ERROR_OK) return retval; /* send base address for read request */ - if ((retval=xscale_send_u32(target, address)) != ERROR_OK) + if ((retval = xscale_send_u32(target, address)) != ERROR_OK) return retval; /* send number of requested data words to be written*/ - if ((retval=xscale_send_u32(target, count)) != ERROR_OK) + if ((retval = xscale_send_u32(target, count)) != ERROR_OK) return retval; /* extract data from host-endian buffer into byte stream */ @@ -2045,16 +1946,16 @@ int xscale_write_memory(struct target_s *target, uint32_t address, uint32_t size } } #endif - if ((retval=xscale_send(target, buffer, count, size)) != ERROR_OK) + if ((retval = xscale_send(target, buffer, count, size)) != ERROR_OK) return retval; /* examine DCSR, to see if Sticky Abort (SA) got set */ - if ((retval=xscale_read_dcsr(target)) != ERROR_OK) + if ((retval = xscale_read_dcsr(target)) != ERROR_OK) return retval; if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1) { /* clear SA bit */ - if ((retval=xscale_send_u32(target, 0x60)) != ERROR_OK) + if ((retval = xscale_send_u32(target, 0x60)) != ERROR_OK) return retval; return ERROR_TARGET_DATA_ABORT; @@ -2063,15 +1964,15 @@ int xscale_write_memory(struct target_s *target, uint32_t address, uint32_t size return ERROR_OK; } -int xscale_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer) +static int xscale_bulk_write_memory(struct target *target, uint32_t address, + uint32_t count, uint8_t *buffer) { return xscale_write_memory(target, address, 4, count, buffer); } -uint32_t xscale_get_ttb(target_t *target) +static uint32_t xscale_get_ttb(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; + struct xscale_common *xscale = target_to_xscale(target); uint32_t ttb; xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_TTB]); @@ -2080,10 +1981,10 @@ uint32_t xscale_get_ttb(target_t *target) return ttb; } -void xscale_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) +static void xscale_disable_mmu_caches(struct target *target, int mmu, + int d_u_cache, int i_cache) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; + struct xscale_common *xscale = target_to_xscale(target); uint32_t cp15_control; /* read cp15 control register */ @@ -2119,10 +2020,10 @@ void xscale_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_c xscale_send_u32(target, 0x53); } -void xscale_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) +static void xscale_enable_mmu_caches(struct target *target, int mmu, + int d_u_cache, int i_cache) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; + struct xscale_common *xscale = target_to_xscale(target); uint32_t cp15_control; /* read cp15 control register */ @@ -2145,11 +2046,11 @@ void xscale_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_ca xscale_send_u32(target, 0x53); } -int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int xscale_set_breakpoint(struct target *target, + struct breakpoint *breakpoint) { int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; + struct xscale_common *xscale = target_to_xscale(target); if (target->state != TARGET_HALTED) { @@ -2218,10 +2119,10 @@ int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } -int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int xscale_add_breakpoint(struct target *target, + struct breakpoint *breakpoint) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; + struct xscale_common *xscale = target_to_xscale(target); if (target->state != TARGET_HALTED) { @@ -2249,11 +2150,11 @@ int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } -int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int xscale_unset_breakpoint(struct target *target, + struct breakpoint *breakpoint) { int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; + struct xscale_common *xscale = target_to_xscale(target); if (target->state != TARGET_HALTED) { @@ -2304,10 +2205,9 @@ int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } -int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int xscale_remove_breakpoint(struct target *target, struct breakpoint *breakpoint) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; + struct xscale_common *xscale = target_to_xscale(target); if (target->state != TARGET_HALTED) { @@ -2326,12 +2226,12 @@ int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } -int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int xscale_set_watchpoint(struct target *target, + struct watchpoint *watchpoint) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; - uint8_t enable=0; - reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON]; + struct xscale_common *xscale = target_to_xscale(target); + uint8_t enable = 0; + struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON]; uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32); if (target->state != TARGET_HALTED) @@ -2382,10 +2282,10 @@ int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) return ERROR_OK; } -int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int xscale_add_watchpoint(struct target *target, + struct watchpoint *watchpoint) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; + struct xscale_common *xscale = target_to_xscale(target); if (target->state != TARGET_HALTED) { @@ -2408,11 +2308,11 @@ int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) return ERROR_OK; } -int xscale_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int xscale_unset_watchpoint(struct target *target, + struct watchpoint *watchpoint) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; - reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON]; + struct xscale_common *xscale = target_to_xscale(target); + struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON]; uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32); if (target->state != TARGET_HALTED) @@ -2444,10 +2344,9 @@ int xscale_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) return ERROR_OK; } -int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int xscale_remove_watchpoint(struct target *target, struct watchpoint *watchpoint) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; + struct xscale_common *xscale = target_to_xscale(target); if (target->state != TARGET_HALTED) { @@ -2465,37 +2364,11 @@ int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) return ERROR_OK; } -void xscale_enable_watchpoints(struct target_s *target) +static int xscale_get_reg(struct reg *reg) { - watchpoint_t *watchpoint = target->watchpoints; - - while (watchpoint) - { - if (watchpoint->set == 0) - xscale_set_watchpoint(target, watchpoint); - watchpoint = watchpoint->next; - } -} - -void xscale_enable_breakpoints(struct target_s *target) -{ - breakpoint_t *breakpoint = target->breakpoints; - - /* set any pending breakpoints */ - while (breakpoint) - { - if (breakpoint->set == 0) - xscale_set_breakpoint(target, breakpoint); - breakpoint = breakpoint->next; - } -} - -int xscale_get_reg(reg_t *reg) -{ - xscale_reg_t *arch_info = reg->arch_info; - target_t *target = arch_info->target; - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; + struct xscale_reg *arch_info = reg->arch_info; + struct target *target = arch_info->target; + struct xscale_common *xscale = target_to_xscale(target); /* DCSR, TX and RX are accessible via JTAG */ if (strcmp(reg->name, "XSCALE_DCSR") == 0) @@ -2536,12 +2409,11 @@ int xscale_get_reg(reg_t *reg) return ERROR_OK; } -int xscale_set_reg(reg_t *reg, uint8_t* buf) +static int xscale_set_reg(struct reg *reg, uint8_t* buf) { - xscale_reg_t *arch_info = reg->arch_info; - target_t *target = arch_info->target; - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; + struct xscale_reg *arch_info = reg->arch_info; + struct target *target = arch_info->target; + struct xscale_common *xscale = target_to_xscale(target); uint32_t value = buf_get_u32(buf, 0, 32); /* DCSR, TX and RX are accessible via JTAG */ @@ -2581,23 +2453,11 @@ int xscale_set_reg(reg_t *reg, uint8_t* buf) return ERROR_OK; } -/* convenience wrapper to access XScale specific registers */ -int xscale_set_reg_u32(reg_t *reg, uint32_t value) +static int xscale_write_dcsr_sw(struct target *target, uint32_t value) { - uint8_t buf[4]; - - buf_set_u32(buf, 0, 32, value); - - return xscale_set_reg(reg, buf); -} - -int xscale_write_dcsr_sw(target_t *target, uint32_t value) -{ - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; - reg_t *dcsr = &xscale->reg_cache->reg_list[XSCALE_DCSR]; - xscale_reg_t *dcsr_arch_info = dcsr->arch_info; + struct xscale_common *xscale = target_to_xscale(target); + struct reg *dcsr = &xscale->reg_cache->reg_list[XSCALE_DCSR]; + struct xscale_reg *dcsr_arch_info = dcsr->arch_info; /* send CP write request (command 0x41) */ xscale_send_u32(target, 0x41); @@ -2612,12 +2472,11 @@ int xscale_write_dcsr_sw(target_t *target, uint32_t value) return ERROR_OK; } -int xscale_read_trace(target_t *target) +static int xscale_read_trace(struct target *target) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; - xscale_trace_data_t **trace_data_p; + struct xscale_common *xscale = target_to_xscale(target); + struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common; + struct xscale_trace_data **trace_data_p; /* 258 words from debug handler * 256 trace buffer entries @@ -2671,12 +2530,12 @@ int xscale_read_trace(target_t *target) for (trace_data_p = &xscale->trace.data; *trace_data_p; trace_data_p = &(*trace_data_p)->next) ; - *trace_data_p = malloc(sizeof(xscale_trace_data_t)); + *trace_data_p = malloc(sizeof(struct xscale_trace_data)); (*trace_data_p)->next = NULL; (*trace_data_p)->chkpt0 = trace_buffer[256]; (*trace_data_p)->chkpt1 = trace_buffer[257]; (*trace_data_p)->last_instruction = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); - (*trace_data_p)->entries = malloc(sizeof(xscale_trace_entry_t) * (256 - j)); + (*trace_data_p)->entries = malloc(sizeof(struct xscale_trace_entry) * (256 - j)); (*trace_data_p)->depth = 256 - j; for (i = j; i < 256; i++) @@ -2691,11 +2550,10 @@ int xscale_read_trace(target_t *target) return ERROR_OK; } -int xscale_read_instruction(target_t *target, arm_instruction_t *instruction) +static int xscale_read_instruction(struct target *target, + struct arm_instruction *instruction) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; + struct xscale_common *xscale = target_to_xscale(target); int i; int section = -1; uint32_t size_read; @@ -2757,7 +2615,8 @@ int xscale_read_instruction(target_t *target, arm_instruction_t *instruction) return ERROR_OK; } -int xscale_branch_address(xscale_trace_data_t *trace_data, int i, uint32_t *target) +static int xscale_branch_address(struct xscale_trace_data *trace_data, + int i, uint32_t *target) { /* if there are less than four entries prior to the indirect branch message * we can't extract the address */ @@ -2772,14 +2631,12 @@ int xscale_branch_address(xscale_trace_data_t *trace_data, int i, uint32_t *targ return 0; } -int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx) +static int xscale_analyze_trace(struct target *target, struct command_context *cmd_ctx) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; + struct xscale_common *xscale = target_to_xscale(target); int next_pc_ok = 0; uint32_t next_pc = 0x0; - xscale_trace_data_t *trace_data = xscale->trace.data; + struct xscale_trace_data *trace_data = xscale->trace.data; int retval; while (trace_data) @@ -2867,7 +2724,7 @@ int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx) if (xscale->trace.pc_ok) { int executed = (trace_data->entries[i].data & 0xf) + rollover * 16; - arm_instruction_t instruction; + struct arm_instruction instruction; if ((exception == 6) || (exception == 7)) { @@ -2939,7 +2796,7 @@ int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx) for (; xscale->trace.current_pc < trace_data->last_instruction; xscale->trace.current_pc += (xscale->trace.core_state == ARMV4_5_STATE_ARM) ? 4 : 2) { - arm_instruction_t instruction; + struct arm_instruction instruction; if ((retval = xscale_read_instruction(target, &instruction)) != ERROR_OK) { /* can't continue tracing with no image available */ @@ -2961,16 +2818,14 @@ int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx) return ERROR_OK; } -void xscale_build_reg_cache(target_t *target) +static void xscale_build_reg_cache(struct target *target) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; - - reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); - xscale_reg_t *arch_info = malloc(sizeof(xscale_reg_arch_info)); + struct xscale_common *xscale = target_to_xscale(target); + struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common; + struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); + struct xscale_reg *arch_info = malloc(sizeof(xscale_reg_arch_info)); int i; - int num_regs = sizeof(xscale_reg_arch_info) / sizeof(xscale_reg_t); + int num_regs = sizeof(xscale_reg_arch_info) / sizeof(struct xscale_reg); (*cache_p) = armv4_5_build_reg_cache(target, armv4_5); armv4_5->core_cache = (*cache_p); @@ -2979,13 +2834,13 @@ void xscale_build_reg_cache(target_t *target) if (xscale_reg_arch_type == -1) xscale_reg_arch_type = register_reg_arch_type(xscale_get_reg, xscale_set_reg); - (*cache_p)->next = malloc(sizeof(reg_cache_t)); + (*cache_p)->next = malloc(sizeof(struct reg_cache)); cache_p = &(*cache_p)->next; /* fill in values for the xscale reg cache */ (*cache_p)->name = "XScale registers"; (*cache_p)->next = NULL; - (*cache_p)->reg_list = malloc(num_regs * sizeof(reg_t)); + (*cache_p)->reg_list = malloc(num_regs * sizeof(struct reg)); (*cache_p)->num_regs = num_regs; for (i = 0; i < num_regs; i++) @@ -2995,8 +2850,6 @@ void xscale_build_reg_cache(target_t *target) (*cache_p)->reg_list[i].dirty = 0; (*cache_p)->reg_list[i].valid = 0; (*cache_p)->reg_list[i].size = 32; - (*cache_p)->reg_list[i].bitfield_desc = NULL; - (*cache_p)->reg_list[i].num_bitfields = 0; (*cache_p)->reg_list[i].arch_info = &arch_info[i]; (*cache_p)->reg_list[i].arch_type = xscale_reg_arch_type; arch_info[i] = xscale_reg_arch_info[i]; @@ -3006,56 +2859,50 @@ void xscale_build_reg_cache(target_t *target) xscale->reg_cache = (*cache_p); } -int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *target) -{ - return ERROR_OK; -} - -int xscale_quit(void) +static int xscale_init_target(struct command_context *cmd_ctx, + struct target *target) { + xscale_build_reg_cache(target); return ERROR_OK; } -int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, jtag_tap_t *tap, const char *variant) +static int xscale_init_arch_info(struct target *target, + struct xscale_common *xscale, struct jtag_tap *tap, const char *variant) { - armv4_5_common_t *armv4_5; + struct arm *armv4_5; uint32_t high_reset_branch, low_reset_branch; int i; armv4_5 = &xscale->armv4_5_common; /* store architecture specfic data (none so far) */ - xscale->arch_info = NULL; xscale->common_magic = XSCALE_COMMON_MAGIC; - /* remember the variant (PXA25x, PXA27x, IXP42x, ...) */ - xscale->variant = strdup(variant); - - /* prepare JTAG information for the new target */ - xscale->jtag_info.tap = tap; - - xscale->jtag_info.dbgrx = 0x02; - xscale->jtag_info.dbgtx = 0x10; - xscale->jtag_info.dcsr = 0x09; - xscale->jtag_info.ldic = 0x07; + /* we don't really *need* variant info ... */ + if (variant) { + int ir_length = 0; + + if (strcmp(variant, "pxa250") == 0 + || strcmp(variant, "pxa255") == 0 + || strcmp(variant, "pxa26x") == 0) + ir_length = 5; + else if (strcmp(variant, "pxa27x") == 0 + || strcmp(variant, "ixp42x") == 0 + || strcmp(variant, "ixp45x") == 0 + || strcmp(variant, "ixp46x") == 0) + ir_length = 7; + else + LOG_WARNING("%s: unrecognized variant %s", + tap->dotted_name, variant); - if ((strcmp(xscale->variant, "pxa250") == 0) || - (strcmp(xscale->variant, "pxa255") == 0) || - (strcmp(xscale->variant, "pxa26x") == 0)) - { - xscale->jtag_info.ir_length = 5; - } - else if ((strcmp(xscale->variant, "pxa27x") == 0) || - (strcmp(xscale->variant, "ixp42x") == 0) || - (strcmp(xscale->variant, "ixp45x") == 0) || - (strcmp(xscale->variant, "ixp46x") == 0)) - { - xscale->jtag_info.ir_length = 7; + if (ir_length && ir_length != tap->ir_length) { + LOG_WARNING("%s: IR length for %s is %d; fixing", + tap->dotted_name, variant, ir_length); + tap->ir_length = ir_length; + } } /* the debug handler isn't installed (and thus not running) at this time */ - xscale->handler_installed = 0; - xscale->handler_running = 0; xscale->handler_address = 0xfe000800; /* clear the vectors we keep locally for reference */ @@ -3124,23 +2971,28 @@ int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, jtag_tap_t return ERROR_OK; } -/* target xscale */ -int xscale_target_create(struct target_s *target, Jim_Interp *interp) +static int xscale_target_create(struct target *target, Jim_Interp *interp) { - xscale_common_t *xscale = calloc(1,sizeof(xscale_common_t)); + struct xscale_common *xscale; - xscale_init_arch_info(target, xscale, target->tap, target->variant); - xscale_build_reg_cache(target); + if (sizeof xscale_debug_handler - 1 > 0x800) { + LOG_ERROR("debug_handler.bin: larger than 2kb"); + return ERROR_FAIL; + } - return ERROR_OK; + xscale = calloc(1, sizeof(*xscale)); + if (!xscale) + return ERROR_FAIL; + + return xscale_init_arch_info(target, xscale, target->tap, + target->variant); } -int xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(xscale_handle_debug_handler_command) { - target_t *target = NULL; - armv4_5_common_t *armv4_5; - xscale_common_t *xscale; - + struct target *target = NULL; + struct xscale_common *xscale; + int retval; uint32_t handler_address; if (argc < 2) @@ -3155,12 +3007,12 @@ int xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, char return ERROR_FAIL; } - if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) - { - return ERROR_FAIL; - } + xscale = target_to_xscale(target); + retval = xscale_verify_pointer(cmd_ctx, xscale); + if (retval != ERROR_OK) + return retval; - handler_address = strtoul(args[1], NULL, 0); + COMMAND_PARSE_NUMBER(u32, args[1], handler_address); if (((handler_address >= 0x800) && (handler_address <= 0x1fef800)) || ((handler_address >= 0xfe000800) && (handler_address <= 0xfffff800))) @@ -3176,12 +3028,11 @@ int xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, char return ERROR_OK; } -int xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(xscale_handle_cache_clean_address_command) { - target_t *target = NULL; - armv4_5_common_t *armv4_5; - xscale_common_t *xscale; - + struct target *target = NULL; + struct xscale_common *xscale; + int retval; uint32_t cache_clean_address; if (argc < 2) @@ -3195,13 +3046,12 @@ int xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx, LOG_ERROR("target '%s' not defined", args[0]); return ERROR_FAIL; } + xscale = target_to_xscale(target); + retval = xscale_verify_pointer(cmd_ctx, xscale); + if (retval != ERROR_OK) + return retval; - if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) - { - return ERROR_FAIL; - } - - cache_clean_address = strtoul(args[1], NULL, 0); + COMMAND_PARSE_NUMBER(u32, args[1], cache_clean_address); if (cache_clean_address & 0xffff) { @@ -3215,34 +3065,33 @@ int xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx, return ERROR_OK; } -int xscale_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(xscale_handle_cache_info_command) { - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - xscale_common_t *xscale; + struct target *target = get_current_target(cmd_ctx); + struct xscale_common *xscale = target_to_xscale(target); + int retval; - if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) - { - return ERROR_OK; - } + retval = xscale_verify_pointer(cmd_ctx, xscale); + if (retval != ERROR_OK) + return retval; return armv4_5_handle_cache_info_command(cmd_ctx, &xscale->armv4_5_mmu.armv4_5_cache); } -static int xscale_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical) +static int xscale_virt2phys(struct target *target, + uint32_t virtual, uint32_t *physical) { - armv4_5_common_t *armv4_5; - xscale_common_t *xscale; - int retval; + struct xscale_common *xscale = target_to_xscale(target); int type; uint32_t cb; int domain; uint32_t ap; - if ((retval = xscale_get_arch_pointers(target, &armv4_5, &xscale)) != ERROR_OK) - { - return retval; + if (xscale->common_magic != XSCALE_COMMON_MAGIC) { + LOG_ERROR(xscale_not); + return ERROR_TARGET_INVALID; } + uint32_t ret = armv4_5_mmu_translate_va(target, &xscale->armv4_5_mmu, virtual, &type, &cb, &domain, &ap); if (type == -1) { @@ -3252,10 +3101,9 @@ static int xscale_virt2phys(struct target_s *target, uint32_t virtual, uint32_t return ERROR_OK; } -static int xscale_mmu(struct target_s *target, int *enabled) +static int xscale_mmu(struct target *target, int *enabled) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; + struct xscale_common *xscale = target_to_xscale(target); if (target->state != TARGET_HALTED) { @@ -3266,20 +3114,19 @@ static int xscale_mmu(struct target_s *target, int *enabled) return ERROR_OK; } -int xscale_handle_mmu_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(xscale_handle_mmu_command) { - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - xscale_common_t *xscale; + struct target *target = get_current_target(cmd_ctx); + struct xscale_common *xscale = target_to_xscale(target); + int retval; - if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) - { - return ERROR_OK; - } + retval = xscale_verify_pointer(cmd_ctx, xscale); + if (retval != ERROR_OK) + return retval; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); + command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } @@ -3302,27 +3149,26 @@ int xscale_handle_mmu_command(command_context_t *cmd_ctx, char *cmd, char **args return ERROR_OK; } -int xscale_handle_idcache_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(xscale_handle_idcache_command) { - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - xscale_common_t *xscale; + struct target *target = get_current_target(cmd_ctx); + struct xscale_common *xscale = target_to_xscale(target); int icache = 0, dcache = 0; + int retval; - if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) - { - return ERROR_OK; - } + retval = xscale_verify_pointer(cmd_ctx, xscale); + if (retval != ERROR_OK) + return retval; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); + command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } - if (strcmp(cmd, "icache") == 0) + if (strcmp(CMD_NAME, "icache") == 0) icache = 1; - else if (strcmp(cmd, "dcache") == 0) + else if (strcmp(CMD_NAME, "dcache") == 0) dcache = 1; if (argc >= 1) @@ -3356,16 +3202,15 @@ int xscale_handle_idcache_command(command_context_t *cmd_ctx, char *cmd, char ** return ERROR_OK; } -int xscale_handle_vector_catch_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(xscale_handle_vector_catch_command) { - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - xscale_common_t *xscale; + struct target *target = get_current_target(cmd_ctx); + struct xscale_common *xscale = target_to_xscale(target); + int retval; - if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) - { - return ERROR_OK; - } + retval = xscale_verify_pointer(cmd_ctx, xscale); + if (retval != ERROR_OK) + return retval; if (argc < 1) { @@ -3373,7 +3218,7 @@ int xscale_handle_vector_catch_command(command_context_t *cmd_ctx, char *cmd, ch } else { - xscale->vector_catch = strtoul(args[0], NULL, 0); + COMMAND_PARSE_NUMBER(u8, args[0], xscale->vector_catch); buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 8, xscale->vector_catch); xscale_write_dcsr(target, -1, -1); } @@ -3384,27 +3229,85 @@ int xscale_handle_vector_catch_command(command_context_t *cmd_ctx, char *cmd, ch } -int xscale_handle_trace_buffer_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(xscale_handle_vector_table_command) { - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - xscale_common_t *xscale; - uint32_t dcsr_value; + struct target *target = get_current_target(cmd_ctx); + struct xscale_common *xscale = target_to_xscale(target); + int err = 0; + int retval; - if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) + retval = xscale_verify_pointer(cmd_ctx, xscale); + if (retval != ERROR_OK) + return retval; + + if (argc == 0) /* print current settings */ { + int idx; + + command_print(cmd_ctx, "active user-set static vectors:"); + for (idx = 1; idx < 8; idx++) + if (xscale->static_low_vectors_set & (1 << idx)) + command_print(cmd_ctx, "low %d: 0x%" PRIx32, idx, xscale->static_low_vectors[idx]); + for (idx = 1; idx < 8; idx++) + if (xscale->static_high_vectors_set & (1 << idx)) + command_print(cmd_ctx, "high %d: 0x%" PRIx32, idx, xscale->static_high_vectors[idx]); return ERROR_OK; } + if (argc != 3) + err = 1; + else + { + int idx; + COMMAND_PARSE_NUMBER(int, args[1], idx); + uint32_t vec; + COMMAND_PARSE_NUMBER(u32, args[2], vec); + + if (idx < 1 || idx >= 8) + err = 1; + + if (!err && strcmp(args[0], "low") == 0) + { + xscale->static_low_vectors_set |= (1<static_low_vectors[idx] = vec; + } + else if (!err && (strcmp(args[0], "high") == 0)) + { + xscale->static_high_vectors_set |= (1<static_high_vectors[idx] = vec; + } + else + err = 1; + } + + if (err) + command_print(cmd_ctx, "usage: xscale vector_table "); + + return ERROR_OK; +} + + +COMMAND_HANDLER(xscale_handle_trace_buffer_command) +{ + struct target *target = get_current_target(cmd_ctx); + struct xscale_common *xscale = target_to_xscale(target); + struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common; + uint32_t dcsr_value; + int retval; + + retval = xscale_verify_pointer(cmd_ctx, xscale); + if (retval != ERROR_OK) + return retval; + if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); + command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } if ((argc >= 1) && (strcmp("enable", args[0]) == 0)) { - xscale_trace_data_t *td, *next_td; + struct xscale_trace_data *td, *next_td; xscale->trace.buffer_enabled = 1; /* free old trace data */ @@ -3427,10 +3330,10 @@ int xscale_handle_trace_buffer_command(struct command_context_s *cmd_ctx, char * if ((argc >= 2) && (strcmp("fill", args[1]) == 0)) { + uint32_t fill = 1; if (argc >= 3) - xscale->trace.buffer_fill = strtoul(args[2], NULL, 0); - else - xscale->trace.buffer_fill = 1; + COMMAND_PARSE_NUMBER(u32, args[2], fill); + xscale->trace.buffer_fill = fill; } else if ((argc >= 2) && (strcmp("wrap", args[1]) == 0)) { @@ -3463,11 +3366,11 @@ int xscale_handle_trace_buffer_command(struct command_context_s *cmd_ctx, char * return ERROR_OK; } -int xscale_handle_trace_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(xscale_handle_trace_image_command) { - target_t *target; - armv4_5_common_t *armv4_5; - xscale_common_t *xscale; + struct target *target = get_current_target(cmd_ctx); + struct xscale_common *xscale = target_to_xscale(target); + int retval; if (argc < 1) { @@ -3475,12 +3378,9 @@ int xscale_handle_trace_image_command(struct command_context_s *cmd_ctx, char *c return ERROR_OK; } - target = get_current_target(cmd_ctx); - - if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) - { - return ERROR_OK; - } + retval = xscale_verify_pointer(cmd_ctx, xscale); + if (retval != ERROR_OK) + return retval; if (xscale->trace.image) { @@ -3489,7 +3389,7 @@ int xscale_handle_trace_image_command(struct command_context_s *cmd_ctx, char *c command_print(cmd_ctx, "previously loaded image found and closed"); } - xscale->trace.image = malloc(sizeof(image_t)); + xscale->trace.image = malloc(sizeof(struct image)); xscale->trace.image->base_address_set = 0; xscale->trace.image->start_address_set = 0; @@ -3497,7 +3397,7 @@ int xscale_handle_trace_image_command(struct command_context_s *cmd_ctx, char *c if (argc >= 2) { xscale->trace.image->base_address_set = 1; - xscale->trace.image->base_address = strtoul(args[1], NULL, 0); + COMMAND_PARSE_NUMBER(int, args[1], xscale->trace.image->base_address); } else { @@ -3514,22 +3414,21 @@ int xscale_handle_trace_image_command(struct command_context_s *cmd_ctx, char *c return ERROR_OK; } -int xscale_handle_dump_trace_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(xscale_handle_dump_trace_command) { - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - xscale_common_t *xscale; - xscale_trace_data_t *trace_data; - fileio_t file; + struct target *target = get_current_target(cmd_ctx); + struct xscale_common *xscale = target_to_xscale(target); + struct xscale_trace_data *trace_data; + struct fileio file; + int retval; - if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) - { - return ERROR_OK; - } + retval = xscale_verify_pointer(cmd_ctx, xscale); + if (retval != ERROR_OK) + return retval; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); + command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } @@ -3572,43 +3471,41 @@ int xscale_handle_dump_trace_command(struct command_context_s *cmd_ctx, char *cm return ERROR_OK; } -int xscale_handle_analyze_trace_buffer_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(xscale_handle_analyze_trace_buffer_command) { - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - xscale_common_t *xscale; + struct target *target = get_current_target(cmd_ctx); + struct xscale_common *xscale = target_to_xscale(target); + int retval; - if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) - { - return ERROR_OK; - } + retval = xscale_verify_pointer(cmd_ctx, xscale); + if (retval != ERROR_OK) + return retval; xscale_analyze_trace(target, cmd_ctx); return ERROR_OK; } -int xscale_handle_cp15(command_context_t *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(xscale_handle_cp15) { - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - xscale_common_t *xscale; + struct target *target = get_current_target(cmd_ctx); + struct xscale_common *xscale = target_to_xscale(target); + int retval; - if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) - { - return ERROR_OK; - } + retval = xscale_verify_pointer(cmd_ctx, xscale); + if (retval != ERROR_OK) + return retval; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); + command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } uint32_t reg_no = 0; - reg_t *reg = NULL; + struct reg *reg = NULL; if (argc > 0) { - reg_no = strtoul(args[0], NULL, 0); + COMMAND_PARSE_NUMBER(u32, args[0], reg_no); /*translate from xscale cp15 register no to openocd register*/ switch (reg_no) { @@ -3654,8 +3551,8 @@ int xscale_handle_cp15(command_context_t *cmd_ctx, char *cmd, char **args, int a } else if (argc == 2) { - - uint32_t value = strtoul(args[1], NULL, 0); + uint32_t value; + COMMAND_PARSE_NUMBER(u32, args[1], value); /* send CP write request (command 0x41) */ xscale_send_u32(target, 0x41); @@ -3677,9 +3574,9 @@ int xscale_handle_cp15(command_context_t *cmd_ctx, char *cmd, char **args, int a return ERROR_OK; } -int xscale_register_commands(struct command_context_s *cmd_ctx) +static int xscale_register_commands(struct command_context *cmd_ctx) { - command_t *xscale_cmd; + struct command *xscale_cmd; xscale_cmd = register_command(cmd_ctx, NULL, "xscale", NULL, COMMAND_ANY, "xscale specific commands"); @@ -3692,8 +3589,9 @@ int xscale_register_commands(struct command_context_s *cmd_ctx) register_command(cmd_ctx, xscale_cmd, "dcache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the DCache"); register_command(cmd_ctx, xscale_cmd, "vector_catch", xscale_handle_vector_catch_command, COMMAND_EXEC, " of vectors that should be catched"); + register_command(cmd_ctx, xscale_cmd, "vector_table", xscale_handle_vector_table_command, COMMAND_EXEC, " set static code for exception handler entry"); - register_command(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, " ['fill' [n]|'wrap']"); + register_command(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, " ['fill' [n]|'wrap']"); register_command(cmd_ctx, xscale_cmd, "dump_trace", xscale_handle_dump_trace_command, COMMAND_EXEC, "dump content of trace buffer to "); register_command(cmd_ctx, xscale_cmd, "analyze_trace", xscale_handle_analyze_trace_buffer_command, COMMAND_EXEC, "analyze content of trace buffer"); @@ -3706,3 +3604,44 @@ int xscale_register_commands(struct command_context_s *cmd_ctx) return ERROR_OK; } + +struct target_type xscale_target = +{ + .name = "xscale", + + .poll = xscale_poll, + .arch_state = xscale_arch_state, + + .target_request_data = NULL, + + .halt = xscale_halt, + .resume = xscale_resume, + .step = xscale_step, + + .assert_reset = xscale_assert_reset, + .deassert_reset = xscale_deassert_reset, + .soft_reset_halt = NULL, + + .get_gdb_reg_list = armv4_5_get_gdb_reg_list, + + .read_memory = xscale_read_memory, + .write_memory = xscale_write_memory, + .bulk_write_memory = xscale_bulk_write_memory, + + .checksum_memory = arm_checksum_memory, + .blank_check_memory = arm_blank_check_memory, + + .run_algorithm = armv4_5_run_algorithm, + + .add_breakpoint = xscale_add_breakpoint, + .remove_breakpoint = xscale_remove_breakpoint, + .add_watchpoint = xscale_add_watchpoint, + .remove_watchpoint = xscale_remove_watchpoint, + + .register_commands = xscale_register_commands, + .target_create = xscale_target_create, + .init_target = xscale_init_target, + + .virt2phys = xscale_virt2phys, + .mmu = xscale_mmu +};