X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fxscale.c;h=e0ce400b46101a5b480467693deccf0757a64db4;hp=1e0ea775305acc5e5c0c8e0ddda33e56fd035372;hb=f1f8d9a6c9b1fd35d79627b568faa2409f13311f;hpb=af949b2531d2a8863d077025db40cbb170d13a63 diff --git a/src/target/xscale.c b/src/target/xscale.c index 1e0ea77530..e0ce400b46 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -27,13 +27,17 @@ #include "config.h" #endif +#include "breakpoints.h" #include "xscale.h" #include "target_type.h" -#include "arm7_9_common.h" +#include "arm_jtag.h" #include "arm_simulator.h" #include "arm_disassembler.h" -#include "time_support.h" +#include +#include "register.h" #include "image.h" +#include "arm_opcodes.h" +#include "armv4_5.h" /* @@ -57,16 +61,16 @@ /* forward declarations */ -static int xscale_resume(struct target_s *, int current, +static int xscale_resume(struct target *, int current, uint32_t address, int handle_breakpoints, int debug_execution); -static int xscale_debug_entry(target_t *); -static int xscale_restore_context(target_t *); -static int xscale_get_reg(reg_t *reg); -static int xscale_set_reg(reg_t *reg, uint8_t *buf); -static int xscale_set_breakpoint(struct target_s *, struct breakpoint *); -static int xscale_set_watchpoint(struct target_s *, struct watchpoint *); -static int xscale_unset_breakpoint(struct target_s *, struct breakpoint *); -static int xscale_read_trace(target_t *); +static int xscale_debug_entry(struct target *); +static int xscale_restore_banked(struct target *); +static int xscale_get_reg(struct reg *reg); +static int xscale_set_reg(struct reg *reg, uint8_t *buf); +static int xscale_set_breakpoint(struct target *, struct breakpoint *); +static int xscale_set_watchpoint(struct target *, struct watchpoint *); +static int xscale_unset_breakpoint(struct target *, struct breakpoint *); +static int xscale_read_trace(struct target *); /* This XScale "debug handler" is loaded into the processor's @@ -132,10 +136,8 @@ static const struct xscale_reg xscale_reg_arch_info[] = {-1, NULL}, /* TXRXCTRL implicit access via JTAG */ }; -static int xscale_reg_arch_type = -1; - /* convenience wrapper to access XScale specific registers */ -static int xscale_set_reg_u32(reg_t *reg, uint32_t value) +static int xscale_set_reg_u32(struct reg *reg, uint32_t value) { uint8_t buf[4]; @@ -146,7 +148,7 @@ static int xscale_set_reg_u32(reg_t *reg, uint32_t value) static const char xscale_not[] = "target is not an XScale"; -static int xscale_verify_pointer(struct command_context_s *cmd_ctx, +static int xscale_verify_pointer(struct command_context *cmd_ctx, struct xscale_common *xscale) { if (xscale->common_magic != XSCALE_COMMON_MAGIC) { @@ -156,10 +158,9 @@ static int xscale_verify_pointer(struct command_context_s *cmd_ctx, return ERROR_OK; } -static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr) +static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr, tap_state_t end_state) { - if (tap == NULL) - return ERROR_FAIL; + assert (tap != NULL); if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) { @@ -167,18 +168,17 @@ static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr) uint8_t scratch[4]; memset(&field, 0, sizeof field); - field.tap = tap; field.num_bits = tap->ir_length; field.out_value = scratch; - buf_set_u32(field.out_value, 0, field.num_bits, new_instr); + buf_set_u32(scratch, 0, field.num_bits, new_instr); - jtag_add_ir_scan(1, &field, jtag_get_end_state()); + jtag_add_ir_scan(tap, &field, end_state); } return ERROR_OK; } -static int xscale_read_dcsr(target_t *target) +static int xscale_read_dcsr(struct target *target) { struct xscale_common *xscale = target_to_xscale(target); int retval; @@ -190,31 +190,29 @@ static int xscale_read_dcsr(target_t *target) uint8_t field2_check_value = 0x0; uint8_t field2_check_mask = 0x1; - jtag_set_end_state(TAP_DRPAUSE); - xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR); + xscale_jtag_set_instr(target->tap, + XSCALE_SELDCSR << xscale->xscale_variant, + TAP_DRPAUSE); buf_set_u32(&field0, 1, 1, xscale->hold_rst); buf_set_u32(&field0, 2, 1, xscale->external_debug_break); memset(&fields, 0, sizeof fields); - fields[0].tap = target->tap; fields[0].num_bits = 3; fields[0].out_value = &field0; uint8_t tmp; fields[0].in_value = &tmp; - fields[1].tap = target->tap; fields[1].num_bits = 32; fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value; - fields[2].tap = target->tap; fields[2].num_bits = 1; fields[2].out_value = &field2; uint8_t tmp2; fields[2].in_value = &tmp2; - jtag_add_dr_scan(3, fields, jtag_get_end_state()); + jtag_add_dr_scan(target->tap, 3, fields, TAP_DRPAUSE); jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask); jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask); @@ -235,9 +233,7 @@ static int xscale_read_dcsr(target_t *target) fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value; fields[1].in_value = NULL; - jtag_set_end_state(TAP_IDLE); - - jtag_add_dr_scan(3, fields, jtag_get_end_state()); + jtag_add_dr_scan(target->tap, 3, fields, TAP_DRPAUSE); /* DANGER!!! this must be here. It will make sure that the arguments * to jtag_set_check_value() does not go out of scope! */ @@ -248,14 +244,15 @@ static int xscale_read_dcsr(target_t *target) static void xscale_getbuf(jtag_callback_data_t arg) { uint8_t *in = (uint8_t *)arg; - *((uint32_t *)in) = buf_get_u32(in, 0, 32); + *((uint32_t *)arg) = buf_get_u32(in, 0, 32); } -static int xscale_receive(target_t *target, uint32_t *buffer, int num_words) +static int xscale_receive(struct target *target, uint32_t *buffer, int num_words) { if (num_words == 0) return ERROR_INVALID_ARGUMENTS; + struct xscale_common *xscale = target_to_xscale(target); int retval = ERROR_OK; tap_state_t path[3]; struct scan_field fields[3]; @@ -275,22 +272,20 @@ static int xscale_receive(target_t *target, uint32_t *buffer, int num_words) memset(&fields, 0, sizeof fields); - fields[0].tap = target->tap; fields[0].num_bits = 3; fields[0].check_value = &field0_check_value; fields[0].check_mask = &field0_check_mask; - fields[1].tap = target->tap; fields[1].num_bits = 32; - fields[2].tap = target->tap; fields[2].num_bits = 1; fields[2].check_value = &field2_check_value; fields[2].check_mask = &field2_check_mask; - jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(target->tap, XSCALE_DBGTX); - jtag_add_runtest(1, jtag_get_end_state()); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */ + xscale_jtag_set_instr(target->tap, + XSCALE_DBGTX << xscale->xscale_variant, + TAP_IDLE); + jtag_add_runtest(1, TAP_IDLE); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */ /* repeat until all words have been collected */ int attempts = 0; @@ -306,7 +301,7 @@ static int xscale_receive(target_t *target, uint32_t *buffer, int num_words) fields[1].in_value = (uint8_t *)(field1 + i); - jtag_add_dr_scan_check(3, fields, jtag_set_end_state(TAP_IDLE)); + jtag_add_dr_scan_check(target->tap, 3, fields, TAP_IDLE); jtag_add_callback(xscale_getbuf, (jtag_callback_data_t)(field1 + i)); @@ -355,7 +350,7 @@ static int xscale_receive(target_t *target, uint32_t *buffer, int num_words) return retval; } -static int xscale_read_tx(target_t *target, int consume) +static int xscale_read_tx(struct target *target, int consume) { struct xscale_common *xscale = target_to_xscale(target); tap_state_t path[3]; @@ -369,9 +364,9 @@ static int xscale_read_tx(target_t *target, int consume) uint8_t field2_check_value = 0x0; uint8_t field2_check_mask = 0x1; - jtag_set_end_state(TAP_IDLE); - - xscale_jtag_set_instr(target->tap, XSCALE_DBGTX); + xscale_jtag_set_instr(target->tap, + XSCALE_DBGTX << xscale->xscale_variant, + TAP_IDLE); path[0] = TAP_DRSELECT; path[1] = TAP_DRCAPTURE; @@ -386,15 +381,12 @@ static int xscale_read_tx(target_t *target, int consume) memset(&fields, 0, sizeof fields); - fields[0].tap = target->tap; fields[0].num_bits = 3; fields[0].in_value = &field0_in; - fields[1].tap = target->tap; fields[1].num_bits = 32; fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value; - fields[2].tap = target->tap; fields[2].num_bits = 1; uint8_t tmp; fields[2].in_value = &tmp; @@ -412,10 +404,10 @@ static int xscale_read_tx(target_t *target, int consume) jtag_add_pathmove(3, path); else { - jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path); + jtag_add_pathmove(ARRAY_SIZE(noconsume_path), noconsume_path); } - jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE)); + jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE); jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask); jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask); @@ -453,7 +445,7 @@ static int xscale_read_tx(target_t *target, int consume) return ERROR_OK; } -static int xscale_write_rx(target_t *target) +static int xscale_write_rx(struct target *target) { struct xscale_common *xscale = target_to_xscale(target); int retval; @@ -467,22 +459,19 @@ static int xscale_write_rx(target_t *target) uint8_t field2_check_value = 0x0; uint8_t field2_check_mask = 0x1; - jtag_set_end_state(TAP_IDLE); - - xscale_jtag_set_instr(target->tap, XSCALE_DBGRX); + xscale_jtag_set_instr(target->tap, + XSCALE_DBGRX << xscale->xscale_variant, + TAP_IDLE); memset(&fields, 0, sizeof fields); - fields[0].tap = target->tap; fields[0].num_bits = 3; fields[0].out_value = &field0_out; fields[0].in_value = &field0_in; - fields[1].tap = target->tap; fields[1].num_bits = 32; fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value; - fields[2].tap = target->tap; fields[2].num_bits = 1; fields[2].out_value = &field2; uint8_t tmp; @@ -495,7 +484,7 @@ static int xscale_write_rx(target_t *target) LOG_DEBUG("polling RX"); for (;;) { - jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE)); + jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE); jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask); jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask); @@ -527,7 +516,7 @@ static int xscale_write_rx(target_t *target) /* set rx_valid */ field2 = 0x1; - jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE)); + jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE); if ((retval = jtag_execute_queue()) != ERROR_OK) { @@ -539,16 +528,17 @@ static int xscale_write_rx(target_t *target) } /* send count elements of size byte to the debug handler */ -static int xscale_send(target_t *target, uint8_t *buffer, int count, int size) +static int xscale_send(struct target *target, uint8_t *buffer, int count, int size) { + struct xscale_common *xscale = target_to_xscale(target); uint32_t t[3]; int bits[3]; int retval; int done_count = 0; - jtag_set_end_state(TAP_IDLE); - - xscale_jtag_set_instr(target->tap, XSCALE_DBGRX); + xscale_jtag_set_instr(target->tap, + XSCALE_DBGRX << xscale->xscale_variant, + TAP_IDLE); bits[0]=3; t[0]=0; @@ -583,13 +573,13 @@ static int xscale_send(target_t *target, uint8_t *buffer, int count, int size) break; default: LOG_ERROR("BUG: size neither 4, 2 nor 1"); - exit(-1); + return ERROR_INVALID_ARGUMENTS; } jtag_add_dr_out(target->tap, 3, bits, t, - jtag_set_end_state(TAP_IDLE)); + TAP_IDLE); buffer += size; } @@ -602,7 +592,7 @@ static int xscale_send(target_t *target, uint8_t *buffer, int count, int size) return ERROR_OK; } -static int xscale_send_u32(target_t *target, uint32_t value) +static int xscale_send_u32(struct target *target, uint32_t value) { struct xscale_common *xscale = target_to_xscale(target); @@ -610,7 +600,7 @@ static int xscale_send_u32(target_t *target, uint32_t value) return xscale_write_rx(target); } -static int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) +static int xscale_write_dcsr(struct target *target, int hold_rst, int ext_dbg_brk) { struct xscale_common *xscale = target_to_xscale(target); int retval; @@ -628,31 +618,29 @@ static int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) if (ext_dbg_brk != -1) xscale->external_debug_break = ext_dbg_brk; - jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR); + xscale_jtag_set_instr(target->tap, + XSCALE_SELDCSR << xscale->xscale_variant, + TAP_IDLE); buf_set_u32(&field0, 1, 1, xscale->hold_rst); buf_set_u32(&field0, 2, 1, xscale->external_debug_break); memset(&fields, 0, sizeof fields); - fields[0].tap = target->tap; fields[0].num_bits = 3; fields[0].out_value = &field0; uint8_t tmp; fields[0].in_value = &tmp; - fields[1].tap = target->tap; fields[1].num_bits = 32; fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value; - fields[2].tap = target->tap; fields[2].num_bits = 1; fields[2].out_value = &field2; uint8_t tmp2; fields[2].in_value = &tmp2; - jtag_add_dr_scan(3, fields, jtag_get_end_state()); + jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE); jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask); jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask); @@ -681,8 +669,9 @@ static unsigned int parity (unsigned int v) return (0x6996 >> v) & 1; } -static int xscale_load_ic(target_t *target, uint32_t va, uint32_t buffer[8]) +static int xscale_load_ic(struct target *target, uint32_t va, uint32_t buffer[8]) { + struct xscale_common *xscale = target_to_xscale(target); uint8_t packet[4]; uint8_t cmd; int word; @@ -691,8 +680,9 @@ static int xscale_load_ic(target_t *target, uint32_t va, uint32_t buffer[8]) LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32 "", va); /* LDIC into IR */ - jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(target->tap, XSCALE_LDIC); + xscale_jtag_set_instr(target->tap, + XSCALE_LDIC << xscale->xscale_variant, + TAP_IDLE); /* CMD is b011 to load a cacheline into the Mini ICache. * Loading into the main ICache is deprecated, and unused. @@ -705,15 +695,13 @@ static int xscale_load_ic(target_t *target, uint32_t va, uint32_t buffer[8]) memset(&fields, 0, sizeof fields); - fields[0].tap = target->tap; fields[0].num_bits = 6; fields[0].out_value = &cmd; - fields[1].tap = target->tap; fields[1].num_bits = 27; fields[1].out_value = packet; - jtag_add_dr_scan(2, fields, jtag_get_end_state()); + jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE); /* rest of packet is a cacheline: 8 instructions, with parity */ fields[0].num_bits = 32; @@ -730,20 +718,22 @@ static int xscale_load_ic(target_t *target, uint32_t va, uint32_t buffer[8]) memcpy(&value, packet, sizeof(uint32_t)); cmd = parity(value); - jtag_add_dr_scan(2, fields, jtag_get_end_state()); + jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE); } return jtag_execute_queue(); } -static int xscale_invalidate_ic_line(target_t *target, uint32_t va) +static int xscale_invalidate_ic_line(struct target *target, uint32_t va) { + struct xscale_common *xscale = target_to_xscale(target); uint8_t packet[4]; uint8_t cmd; struct scan_field fields[2]; - jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(target->tap, XSCALE_LDIC); + xscale_jtag_set_instr(target->tap, + XSCALE_LDIC << xscale->xscale_variant, + TAP_IDLE); /* CMD for invalidate IC line b000, bits [6:4] b000 */ buf_set_u32(&cmd, 0, 6, 0x0); @@ -753,20 +743,18 @@ static int xscale_invalidate_ic_line(target_t *target, uint32_t va) memset(&fields, 0, sizeof fields); - fields[0].tap = target->tap; fields[0].num_bits = 6; fields[0].out_value = &cmd; - fields[1].tap = target->tap; fields[1].num_bits = 27; fields[1].out_value = packet; - jtag_add_dr_scan(2, fields, jtag_get_end_state()); + jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE); return ERROR_OK; } -static int xscale_update_vectors(target_t *target) +static int xscale_update_vectors(struct target *target) { struct xscale_common *xscale = target_to_xscale(target); int i; @@ -830,10 +818,10 @@ static int xscale_update_vectors(target_t *target) return ERROR_OK; } -static int xscale_arch_state(struct target_s *target) +static int xscale_arch_state(struct target *target) { struct xscale_common *xscale = target_to_xscale(target); - struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common; + struct arm *armv4_5 = &xscale->armv4_5_common; static const char *state[] = { @@ -845,21 +833,14 @@ static int xscale_arch_state(struct target_s *target) "", "\n(processor reset)", "\n(trace buffer full)" }; - if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) + if (armv4_5->common_magic != ARM_COMMON_MAGIC) { LOG_ERROR("BUG: called for a non-ARMv4/5 target"); - exit(-1); + return ERROR_INVALID_ARGUMENTS; } - LOG_USER("target halted in %s state due to %s, current mode: %s\n" - "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n" - "MMU: %s, D-Cache: %s, I-Cache: %s" - "%s", - armv4_5_state_strings[armv4_5->core_state], - Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name , - armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], - buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), - buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), + arm_arch_state(target); + LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s%s", state[xscale->armv4_5_mmu.mmu_enabled], state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], state[xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled], @@ -868,7 +849,7 @@ static int xscale_arch_state(struct target_s *target) return ERROR_OK; } -static int xscale_poll(target_t *target) +static int xscale_poll(struct target *target) { int retval = ERROR_OK; @@ -908,13 +889,13 @@ static int xscale_poll(target_t *target) return retval; } -static int xscale_debug_entry(target_t *target) +static int xscale_debug_entry(struct target *target) { struct xscale_common *xscale = target_to_xscale(target); - struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common; + struct arm *armv4_5 = &xscale->armv4_5_common; uint32_t pc; uint32_t buffer[10]; - int i; + unsigned i; int retval; uint32_t moe; @@ -934,9 +915,9 @@ static int xscale_debug_entry(target_t *target) LOG_DEBUG("r0: 0x%8.8" PRIx32 "", buffer[0]); /* move pc from buffer to register cache */ - buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, buffer[1]); - armv4_5->core_cache->reg_list[15].dirty = 1; - armv4_5->core_cache->reg_list[15].valid = 1; + buf_set_u32(armv4_5->pc->value, 0, 32, buffer[1]); + armv4_5->pc->dirty = 1; + armv4_5->pc->valid = 1; LOG_DEBUG("pc: 0x%8.8" PRIx32 "", buffer[1]); /* move data from buffer to register cache */ @@ -948,36 +929,24 @@ static int xscale_debug_entry(target_t *target) LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, buffer[i + 1]); } - buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, buffer[9]); - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; + arm_set_cpsr(armv4_5, buffer[9]); LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]); - armv4_5->core_mode = buffer[9] & 0x1f; - if (armv4_5_mode_to_number(armv4_5->core_mode) == -1) + if (!is_arm_mode(armv4_5->core_mode)) { target->state = TARGET_UNKNOWN; LOG_ERROR("cpsr contains invalid mode value - communication failure"); return ERROR_TARGET_FAILURE; } - LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]); - - if (buffer[9] & 0x20) - armv4_5->core_state = ARMV4_5_STATE_THUMB; - else - armv4_5->core_state = ARMV4_5_STATE_ARM; - - - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) - return ERROR_FAIL; + LOG_DEBUG("target entered debug state in %s mode", + arm_mode_name(armv4_5->core_mode)); /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */ - if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS)) - { + if (armv4_5->spsr) { xscale_receive(target, buffer, 8); - buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, buffer[7]); - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1; + buf_set_u32(armv4_5->spsr->value, 0, 32, buffer[7]); + armv4_5->spsr->dirty = false; + armv4_5->spsr->valid = true; } else { @@ -985,20 +954,27 @@ static int xscale_debug_entry(target_t *target) xscale_receive(target, buffer, 7); } - /* move data from buffer to register cache */ + /* move data from buffer to right banked register in cache */ for (i = 8; i <= 14; i++) { - buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, buffer[i - 8]); - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1; + struct reg *r = arm_reg_current(armv4_5, i); + + buf_set_u32(r->value, 0, 32, buffer[i - 8]); + r->dirty = false; + r->valid = true; } + /* mark xscale regs invalid to ensure they are retrieved from the + * debug handler if requested */ + for (i = 0; i < xscale->reg_cache->num_regs; i++) + xscale->reg_cache->reg_list[i].valid = 0; + /* examine debug reason */ xscale_read_dcsr(target); moe = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 2, 3); /* stored PC (for calculating fixup) */ - pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); + pc = buf_get_u32(armv4_5->pc->value, 0, 32); switch (moe) { @@ -1045,7 +1021,7 @@ static int xscale_debug_entry(target_t *target) } /* apply PC fixup */ - buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc); + buf_set_u32(armv4_5->pc->value, 0, 32, pc); /* on the first debug entry, identify cache type */ if (xscale->armv4_5_mmu.armv4_5_cache.ctype == -1) @@ -1088,7 +1064,7 @@ static int xscale_debug_entry(target_t *target) return ERROR_OK; } -static int xscale_halt(target_t *target) +static int xscale_halt(struct target *target) { struct xscale_common *xscale = target_to_xscale(target); @@ -1122,10 +1098,10 @@ static int xscale_halt(target_t *target) return ERROR_OK; } -static int xscale_enable_single_step(struct target_s *target, uint32_t next_pc) +static int xscale_enable_single_step(struct target *target, uint32_t next_pc) { struct xscale_common *xscale = target_to_xscale(target); - reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0]; + struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0]; int retval; if (xscale->ibcr0_used) @@ -1149,10 +1125,10 @@ static int xscale_enable_single_step(struct target_s *target, uint32_t next_pc) return ERROR_OK; } -static int xscale_disable_single_step(struct target_s *target) +static int xscale_disable_single_step(struct target *target) { struct xscale_common *xscale = target_to_xscale(target); - reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0]; + struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0]; int retval; if ((retval = xscale_set_reg_u32(ibcr0, 0x0)) != ERROR_OK) @@ -1161,7 +1137,7 @@ static int xscale_disable_single_step(struct target_s *target) return ERROR_OK; } -static void xscale_enable_watchpoints(struct target_s *target) +static void xscale_enable_watchpoints(struct target *target) { struct watchpoint *watchpoint = target->watchpoints; @@ -1173,7 +1149,7 @@ static void xscale_enable_watchpoints(struct target_s *target) } } -static void xscale_enable_breakpoints(struct target_s *target) +static void xscale_enable_breakpoints(struct target *target) { struct breakpoint *breakpoint = target->breakpoints; @@ -1186,11 +1162,11 @@ static void xscale_enable_breakpoints(struct target_s *target) } } -static int xscale_resume(struct target_s *target, int current, +static int xscale_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) { struct xscale_common *xscale = target_to_xscale(target); - struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common; + struct arm *armv4_5 = &xscale->armv4_5_common; struct breakpoint *breakpoint = target->breakpoints; uint32_t current_pc; int retval; @@ -1215,23 +1191,26 @@ static int xscale_resume(struct target_s *target, int current, /* current = 1: continue on current pc, otherwise continue at
*/ if (!current) - buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address); + buf_set_u32(armv4_5->pc->value, 0, 32, address); - current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); + current_pc = buf_get_u32(armv4_5->pc->value, 0, 32); /* if we're at the reset vector, we have to simulate the branch */ if (current_pc == 0x0) { arm_simulate_step(target, NULL); - current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); + current_pc = buf_get_u32(armv4_5->pc->value, 0, 32); } /* the front-end may request us not to handle breakpoints */ if (handle_breakpoints) { - if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)))) + breakpoint = breakpoint_find(target, + buf_get_u32(armv4_5->pc->value, 0, 32)); + if (breakpoint != NULL) { uint32_t next_pc; + int saved_trace_buffer_enabled; /* there's a breakpoint at the current PC, we have to step over it */ LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address); @@ -1249,21 +1228,16 @@ static int xscale_resume(struct target_s *target, int current, xscale_enable_single_step(target, next_pc); /* restore banked registers */ - xscale_restore_context(target); + retval = xscale_restore_banked(target); - /* send resume request (command 0x30 or 0x31) - * clean the trace buffer if it is to be enabled (0x62) */ - if (xscale->trace.buffer_enabled) - { - xscale_send_u32(target, 0x62); - xscale_send_u32(target, 0x31); - } - else - xscale_send_u32(target, 0x30); + /* send resume request */ + xscale_send_u32(target, 0x30); /* send CPSR */ - xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); - LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); + xscale_send_u32(target, + buf_get_u32(armv4_5->cpsr->value, 0, 32)); + LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32, + buf_get_u32(armv4_5->cpsr->value, 0, 32)); for (i = 7; i >= 0; i--) { @@ -1273,12 +1247,21 @@ static int xscale_resume(struct target_s *target, int current, } /* send PC */ - xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); - LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); + xscale_send_u32(target, + buf_get_u32(armv4_5->pc->value, 0, 32)); + LOG_DEBUG("writing PC with value 0x%8.8" PRIx32, + buf_get_u32(armv4_5->pc->value, 0, 32)); + + /* disable trace data collection in xscale_debug_entry() */ + saved_trace_buffer_enabled = xscale->trace.buffer_enabled; + xscale->trace.buffer_enabled = 0; /* wait for and process debug entry */ xscale_debug_entry(target); + /* re-enable trace buffer, if enabled previously */ + xscale->trace.buffer_enabled = saved_trace_buffer_enabled; + LOG_DEBUG("disable single-step"); xscale_disable_single_step(target); @@ -1292,7 +1275,7 @@ static int xscale_resume(struct target_s *target, int current, xscale_enable_watchpoints(target); /* restore banked registers */ - xscale_restore_context(target); + retval = xscale_restore_banked(target); /* send resume request (command 0x30 or 0x31) * clean the trace buffer if it is to be enabled (0x62) */ @@ -1305,8 +1288,9 @@ static int xscale_resume(struct target_s *target, int current, xscale_send_u32(target, 0x30); /* send CPSR */ - xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); - LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); + xscale_send_u32(target, buf_get_u32(armv4_5->cpsr->value, 0, 32)); + LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32, + buf_get_u32(armv4_5->cpsr->value, 0, 32)); for (i = 7; i >= 0; i--) { @@ -1316,15 +1300,16 @@ static int xscale_resume(struct target_s *target, int current, } /* send PC */ - xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); - LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); + xscale_send_u32(target, buf_get_u32(armv4_5->pc->value, 0, 32)); + LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32, + buf_get_u32(armv4_5->pc->value, 0, 32)); target->debug_reason = DBG_REASON_NOTHALTED; if (!debug_execution) { /* registers are now invalid */ - armv4_5_invalidate_core_regs(target); + register_cache_invalidate(armv4_5->core_cache); target->state = TARGET_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_RESUMED); } @@ -1339,11 +1324,11 @@ static int xscale_resume(struct target_s *target, int current, return ERROR_OK; } -static int xscale_step_inner(struct target_s *target, int current, +static int xscale_step_inner(struct target *target, int current, uint32_t address, int handle_breakpoints) { struct xscale_common *xscale = target_to_xscale(target); - struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common; + struct arm *armv4_5 = &xscale->armv4_5_common; uint32_t next_pc; int retval; int i; @@ -1354,7 +1339,7 @@ static int xscale_step_inner(struct target_s *target, int current, if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK) { uint32_t current_opcode, current_pc; - current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); + current_pc = buf_get_u32(armv4_5->pc->value, 0, 32); target_read_u32(target, current_pc, ¤t_opcode); LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode); @@ -1366,7 +1351,7 @@ static int xscale_step_inner(struct target_s *target, int current, return retval; /* restore banked registers */ - if ((retval = xscale_restore_context(target)) != ERROR_OK) + if ((retval = xscale_restore_banked(target)) != ERROR_OK) return retval; /* send resume request (command 0x30 or 0x31) @@ -1383,9 +1368,12 @@ static int xscale_step_inner(struct target_s *target, int current, return retval; /* send CPSR */ - if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32))) != ERROR_OK) + retval = xscale_send_u32(target, + buf_get_u32(armv4_5->cpsr->value, 0, 32)); + if (retval != ERROR_OK) return retval; - LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); + LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32, + buf_get_u32(armv4_5->cpsr->value, 0, 32)); for (i = 7; i >= 0; i--) { @@ -1396,15 +1384,17 @@ static int xscale_step_inner(struct target_s *target, int current, } /* send PC */ - if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))) != ERROR_OK) + retval = xscale_send_u32(target, + buf_get_u32(armv4_5->pc->value, 0, 32)); + if (retval != ERROR_OK) return retval; - LOG_DEBUG("writing PC with value 0x%8.8" PRIx32, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); + LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32, + buf_get_u32(armv4_5->pc->value, 0, 32)); target_call_event_callbacks(target, TARGET_EVENT_RESUMED); /* registers are now invalid */ - if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK) - return retval; + register_cache_invalidate(armv4_5->core_cache); /* wait for and process debug entry */ if ((retval = xscale_debug_entry(target)) != ERROR_OK) @@ -1419,11 +1409,11 @@ static int xscale_step_inner(struct target_s *target, int current, return ERROR_OK; } -static int xscale_step(struct target_s *target, int current, +static int xscale_step(struct target *target, int current, uint32_t address, int handle_breakpoints) { - struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); - struct breakpoint *breakpoint = target->breakpoints; + struct arm *armv4_5 = target_to_arm(target); + struct breakpoint *breakpoint = NULL; uint32_t current_pc; int retval; @@ -1436,16 +1426,16 @@ static int xscale_step(struct target_s *target, int current, /* current = 1: continue on current pc, otherwise continue at
*/ if (!current) - buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address); + buf_set_u32(armv4_5->pc->value, 0, 32, address); - current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); + current_pc = buf_get_u32(armv4_5->pc->value, 0, 32); /* if we're at the reset vector, we have to simulate the step */ if (current_pc == 0x0) { if ((retval = arm_simulate_step(target, NULL)) != ERROR_OK) return retval; - current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); + current_pc = buf_get_u32(armv4_5->pc->value, 0, 32); target->debug_reason = DBG_REASON_SINGLESTEP; target_call_event_callbacks(target, TARGET_EVENT_HALTED); @@ -1455,11 +1445,13 @@ static int xscale_step(struct target_s *target, int current, /* the front-end may request us not to handle breakpoints */ if (handle_breakpoints) - if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)))) - { - if ((retval = xscale_unset_breakpoint(target, breakpoint)) != ERROR_OK) - return retval; - } + breakpoint = breakpoint_find(target, + buf_get_u32(armv4_5->pc->value, 0, 32)); + if (breakpoint != NULL) { + retval = xscale_unset_breakpoint(target, breakpoint); + if (retval != ERROR_OK) + return retval; + } retval = xscale_step_inner(target, current, address, handle_breakpoints); @@ -1474,7 +1466,7 @@ static int xscale_step(struct target_s *target, int current, } -static int xscale_assert_reset(target_t *target) +static int xscale_assert_reset(struct target *target) { struct xscale_common *xscale = target_to_xscale(target); @@ -1484,8 +1476,9 @@ static int xscale_assert_reset(target_t *target) /* select DCSR instruction (set endstate to R-T-I to ensure we don't * end up in T-L-R, which would reset JTAG */ - jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR); + xscale_jtag_set_instr(target->tap, + XSCALE_SELDCSR << xscale->xscale_variant, + TAP_IDLE); /* set Hold reset, Halt mode and Trap Reset */ buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1); @@ -1493,7 +1486,7 @@ static int xscale_assert_reset(target_t *target) xscale_write_dcsr(target, 1, 0); /* select BYPASS, because having DCSR selected caused problems on the PXA27x */ - xscale_jtag_set_instr(target->tap, 0x7f); + xscale_jtag_set_instr(target->tap, ~0, TAP_IDLE); jtag_execute_queue(); /* assert reset */ @@ -1515,7 +1508,7 @@ static int xscale_assert_reset(target_t *target) return ERROR_OK; } -static int xscale_deassert_reset(target_t *target) +static int xscale_deassert_reset(struct target *target) { struct xscale_common *xscale = target_to_xscale(target); struct breakpoint *breakpoint = target->breakpoints; @@ -1540,7 +1533,7 @@ static int xscale_deassert_reset(target_t *target) breakpoint = breakpoint->next; } - armv4_5_invalidate_core_regs(target); + register_cache_invalidate(xscale->armv4_5_common.core_cache); /* FIXME mark hardware watchpoints got unset too. Also, * at least some of the XScale registers are invalid... @@ -1563,7 +1556,7 @@ static int xscale_deassert_reset(target_t *target) /* wait 300ms; 150 and 100ms were not enough */ jtag_add_sleep(300*1000); - jtag_add_runtest(2030, jtag_set_end_state(TAP_IDLE)); + jtag_add_runtest(2030, TAP_IDLE); jtag_execute_queue(); /* set Hold reset, Halt mode and Trap Reset */ @@ -1620,7 +1613,7 @@ static int xscale_deassert_reset(target_t *target) if (retval != ERROR_OK) return retval; - jtag_add_runtest(30, jtag_set_end_state(TAP_IDLE)); + jtag_add_runtest(30, TAP_IDLE); jtag_add_sleep(100000); @@ -1649,23 +1642,25 @@ static int xscale_deassert_reset(target_t *target) return ERROR_OK; } -static int xscale_read_core_reg(struct target_s *target, int num, - enum armv4_5_mode mode) +static int xscale_read_core_reg(struct target *target, struct reg *r, + int num, enum arm_mode mode) { + /** \todo add debug handler support for core register reads */ LOG_ERROR("not implemented"); return ERROR_OK; } -static int xscale_write_core_reg(struct target_s *target, int num, - enum armv4_5_mode mode, uint32_t value) +static int xscale_write_core_reg(struct target *target, struct reg *r, + int num, enum arm_mode mode, uint32_t value) { + /** \todo add debug handler support for core register writes */ LOG_ERROR("not implemented"); return ERROR_OK; } -static int xscale_full_context(target_t *target) +static int xscale_full_context(struct target *target) { - struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_arm(target); uint32_t *buffer; @@ -1687,50 +1682,56 @@ static int xscale_full_context(target_t *target) */ for (i = 1; i < 7; i++) { - int valid = 1; + enum arm_mode mode = armv4_5_number_to_mode(i); + bool valid = true; + struct reg *r; + + if (mode == ARM_MODE_USR) + continue; /* check if there are invalid registers in the current mode */ - for (j = 0; j <= 16; j++) + for (j = 0; valid && j <= 16; j++) { - if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0) - valid = 0; + if (!ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, + mode, j).valid) + valid = false; } + if (valid) + continue; - if (!valid) - { - uint32_t tmp_cpsr; - - /* request banked registers */ - xscale_send_u32(target, 0x0); + /* request banked registers */ + xscale_send_u32(target, 0x0); - tmp_cpsr = 0x0; - tmp_cpsr |= armv4_5_number_to_mode(i); - tmp_cpsr |= 0xc0; /* I/F bits */ + /* send CPSR for desired bank mode */ + xscale_send_u32(target, mode | 0xc0 /* I/F bits */); - /* send CPSR for desired mode */ - xscale_send_u32(target, tmp_cpsr); + /* get banked registers: r8 to r14; and SPSR + * except in USR/SYS mode + */ + if (mode != ARM_MODE_SYS) { + /* SPSR */ + r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, + mode, 16); + + xscale_receive(target, buffer, 8); + + buf_set_u32(r->value, 0, 32, buffer[7]); + r->dirty = false; + r->valid = true; + } else { + xscale_receive(target, buffer, 7); + } - /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */ - if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS)) - { - xscale_receive(target, buffer, 8); - buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, buffer[7]); - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1; - } - else - { - xscale_receive(target, buffer, 7); - } + /* move data from buffer to register cache */ + for (j = 8; j <= 14; j++) + { + r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, + mode, j); - /* move data from buffer to register cache */ - for (j = 8; j <= 14; j++) - { - buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value, 0, 32, buffer[j - 8]); - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1; - } + buf_set_u32(r->value, 0, 32, buffer[j - 8]); + r->dirty = false; + r->valid = true; } } @@ -1739,9 +1740,9 @@ static int xscale_full_context(target_t *target) return ERROR_OK; } -static int xscale_restore_context(target_t *target) +static int xscale_restore_banked(struct target *target) { - struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_arm(target); int i, j; @@ -1752,61 +1753,67 @@ static int xscale_restore_context(target_t *target) } /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS) - * we can't enter User mode on an XScale (unpredictable), - * but User shares registers with SYS - */ + * and check if any banked registers need to be written. Ignore + * USR mode (number 0) in favor of SYS; we can't enter User mode on + * an XScale (unpredictable), but they share all registers. + */ for (i = 1; i < 7; i++) { - int dirty = 0; + enum arm_mode mode = armv4_5_number_to_mode(i); + struct reg *r; - /* check if there are invalid registers in the current mode - */ + if (mode == ARM_MODE_USR) + continue; + + /* check if there are dirty registers in this mode */ for (j = 8; j <= 14; j++) { - if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty == 1) - dirty = 1; + if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, + mode, j).dirty) + goto dirty; } /* if not USR/SYS, check if the SPSR needs to be written */ - if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS)) + if (mode != ARM_MODE_SYS) { - if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty == 1) - dirty = 1; + if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, + mode, 16).dirty) + goto dirty; } - if (dirty) - { - uint32_t tmp_cpsr; - - /* send banked registers */ - xscale_send_u32(target, 0x1); + /* there's nothing to flush for this mode */ + continue; - tmp_cpsr = 0x0; - tmp_cpsr |= armv4_5_number_to_mode(i); - tmp_cpsr |= 0xc0; /* I/F bits */ +dirty: + /* command 0x1: "send banked registers" */ + xscale_send_u32(target, 0x1); - /* send CPSR for desired mode */ - xscale_send_u32(target, tmp_cpsr); + /* send CPSR for desired mode */ + xscale_send_u32(target, mode | 0xc0 /* I/F bits */); - /* send banked registers, r8 to r14, and spsr if not in USR/SYS mode */ - for (j = 8; j <= 14; j++) - { - xscale_send_u32(target, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, j).value, 0, 32)); - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0; - } + /* send r8 to r14/lr ... only FIQ needs more than r13..r14, + * but this protocol doesn't understand that nuance. + */ + for (j = 8; j <= 14; j++) { + r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, + mode, j); + xscale_send_u32(target, buf_get_u32(r->value, 0, 32)); + r->dirty = false; + } - if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS)) - { - xscale_send_u32(target, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32)); - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0; - } + /* send spsr if not in USR/SYS mode */ + if (mode != ARM_MODE_SYS) { + r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, + mode, 16); + xscale_send_u32(target, buf_get_u32(r->value, 0, 32)); + r->dirty = false; } } return ERROR_OK; } -static int xscale_read_memory(struct target_s *target, uint32_t address, +static int xscale_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { struct xscale_common *xscale = target_to_xscale(target); @@ -1863,8 +1870,8 @@ static int xscale_read_memory(struct target_s *target, uint32_t address, *buffer++ = buf32[i] & 0xff; break; default: - LOG_ERROR("should never get here"); - exit(-1); + LOG_ERROR("invalid read size"); + return ERROR_INVALID_ARGUMENTS; } } @@ -1885,7 +1892,22 @@ static int xscale_read_memory(struct target_s *target, uint32_t address, return ERROR_OK; } -static int xscale_write_memory(struct target_s *target, uint32_t address, +static int xscale_read_phys_memory(struct target *target, uint32_t address, + uint32_t size, uint32_t count, uint8_t *buffer) +{ + struct xscale_common *xscale = target_to_xscale(target); + + /* with MMU inactive, there are only physical addresses */ + if (!xscale->armv4_5_mmu.mmu_enabled) + return xscale_read_memory(target, address, size, count, buffer); + + /** \todo: provide a non-stub implementation of this routine. */ + LOG_ERROR("%s: %s is not implemented. Disable MMU?", + target_name(target), __func__); + return ERROR_FAIL; +} + +static int xscale_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { struct xscale_common *xscale = target_to_xscale(target); @@ -1957,37 +1979,61 @@ static int xscale_write_memory(struct target_s *target, uint32_t address, if ((retval = xscale_send_u32(target, 0x60)) != ERROR_OK) return retval; + LOG_ERROR("data abort writing memory"); return ERROR_TARGET_DATA_ABORT; } return ERROR_OK; } -static int xscale_bulk_write_memory(target_t *target, uint32_t address, +static int xscale_write_phys_memory(struct target *target, uint32_t address, + uint32_t size, uint32_t count, uint8_t *buffer) +{ + struct xscale_common *xscale = target_to_xscale(target); + + /* with MMU inactive, there are only physical addresses */ + if (!xscale->armv4_5_mmu.mmu_enabled) + return xscale_read_memory(target, address, size, count, buffer); + + /** \todo: provide a non-stub implementation of this routine. */ + LOG_ERROR("%s: %s is not implemented. Disable MMU?", + target_name(target), __func__); + return ERROR_FAIL; +} + +static int xscale_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer) { return xscale_write_memory(target, address, 4, count, buffer); } -static uint32_t xscale_get_ttb(target_t *target) +static int xscale_get_ttb(struct target *target, uint32_t *result) { struct xscale_common *xscale = target_to_xscale(target); uint32_t ttb; + int retval; - xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_TTB]); + retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_TTB]); + if (retval != ERROR_OK) + return retval; ttb = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_TTB].value, 0, 32); - return ttb; + *result = ttb; + + return ERROR_OK; } -static void xscale_disable_mmu_caches(target_t *target, int mmu, +static int xscale_disable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache) { struct xscale_common *xscale = target_to_xscale(target); uint32_t cp15_control; + int retval; /* read cp15 control register */ - xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]); + retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]); + if (retval !=ERROR_OK) + return retval; cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32); if (mmu) @@ -1996,11 +2042,17 @@ static void xscale_disable_mmu_caches(target_t *target, int mmu, if (d_u_cache) { /* clean DCache */ - xscale_send_u32(target, 0x50); - xscale_send_u32(target, xscale->cache_clean_address); + retval = xscale_send_u32(target, 0x50); + if (retval !=ERROR_OK) + return retval; + retval = xscale_send_u32(target, xscale->cache_clean_address); + if (retval !=ERROR_OK) + return retval; /* invalidate DCache */ - xscale_send_u32(target, 0x51); + retval = xscale_send_u32(target, 0x51); + if (retval !=ERROR_OK) + return retval; cp15_control &= ~0x4U; } @@ -2008,25 +2060,33 @@ static void xscale_disable_mmu_caches(target_t *target, int mmu, if (i_cache) { /* invalidate ICache */ - xscale_send_u32(target, 0x52); + retval = xscale_send_u32(target, 0x52); + if (retval !=ERROR_OK) + return retval; cp15_control &= ~0x1000U; } /* write new cp15 control register */ - xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control); + retval = xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control); + if (retval !=ERROR_OK) + return retval; /* execute cpwait to ensure outstanding operations complete */ - xscale_send_u32(target, 0x53); + retval = xscale_send_u32(target, 0x53); + return retval; } -static void xscale_enable_mmu_caches(target_t *target, int mmu, +static int xscale_enable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache) { struct xscale_common *xscale = target_to_xscale(target); uint32_t cp15_control; + int retval; /* read cp15 control register */ - xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]); + retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]); + if (retval !=ERROR_OK) + return retval; cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32); if (mmu) @@ -2039,13 +2099,16 @@ static void xscale_enable_mmu_caches(target_t *target, int mmu, cp15_control |= 0x1000U; /* write new cp15 control register */ - xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control); + retval = xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control); + if (retval !=ERROR_OK) + return retval; /* execute cpwait to ensure outstanding operations complete */ - xscale_send_u32(target, 0x53); + retval = xscale_send_u32(target, 0x53); + return retval; } -static int xscale_set_breakpoint(struct target_s *target, +static int xscale_set_breakpoint(struct target *target, struct breakpoint *breakpoint) { int retval; @@ -2079,9 +2142,9 @@ static int xscale_set_breakpoint(struct target_s *target, breakpoint->set = 2; /* breakpoint set on second breakpoint register */ } else - { + { /* bug: availability previously verified in xscale_add_breakpoint() */ LOG_ERROR("BUG: no hardware comparator available"); - return ERROR_OK; + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } } else if (breakpoint->type == BKPT_SOFT) @@ -2093,7 +2156,7 @@ static int xscale_set_breakpoint(struct target_s *target, { return retval; } - /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */ + /* write the bkpt instruction in target endianness (arm7_9->arm_bkpt is host endian) */ if ((retval = target_write_u32(target, breakpoint->address, xscale->arm_bkpt)) != ERROR_OK) { return retval; @@ -2106,38 +2169,37 @@ static int xscale_set_breakpoint(struct target_s *target, { return retval; } - /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */ - if ((retval = target_write_u32(target, breakpoint->address, xscale->thumb_bkpt)) != ERROR_OK) + /* write the bkpt instruction in target endianness (arm7_9->arm_bkpt is host endian) */ + if ((retval = target_write_u16(target, breakpoint->address, xscale->thumb_bkpt)) != ERROR_OK) { return retval; } } breakpoint->set = 1; + + xscale_send_u32(target, 0x50); /* clean dcache */ + xscale_send_u32(target, xscale->cache_clean_address); + xscale_send_u32(target, 0x51); /* invalidate dcache */ + xscale_send_u32(target, 0x52); /* invalidate icache and flush fetch buffers */ } return ERROR_OK; } -static int xscale_add_breakpoint(struct target_s *target, +static int xscale_add_breakpoint(struct target *target, struct breakpoint *breakpoint) { struct xscale_common *xscale = target_to_xscale(target); - if (target->state != TARGET_HALTED) - { - LOG_WARNING("target not halted"); - return ERROR_TARGET_NOT_HALTED; - } - if ((breakpoint->type == BKPT_HARD) && (xscale->ibcr_available < 1)) { - LOG_INFO("no breakpoint unit available for hardware breakpoint"); + LOG_ERROR("no breakpoint unit available for hardware breakpoint"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } if ((breakpoint->length != 2) && (breakpoint->length != 4)) { - LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported"); + LOG_ERROR("only breakpoints of two (Thumb) or four (ARM) bytes length supported"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -2146,10 +2208,10 @@ static int xscale_add_breakpoint(struct target_s *target, xscale->ibcr_available--; } - return ERROR_OK; + return xscale_set_breakpoint(target, breakpoint); } -static int xscale_unset_breakpoint(struct target_s *target, +static int xscale_unset_breakpoint(struct target *target, struct breakpoint *breakpoint) { int retval; @@ -2199,18 +2261,23 @@ static int xscale_unset_breakpoint(struct target_s *target, } } breakpoint->set = 0; + + xscale_send_u32(target, 0x50); /* clean dcache */ + xscale_send_u32(target, xscale->cache_clean_address); + xscale_send_u32(target, 0x51); /* invalidate dcache */ + xscale_send_u32(target, 0x52); /* invalidate icache and flush fetch buffers */ } return ERROR_OK; } -static int xscale_remove_breakpoint(struct target_s *target, struct breakpoint *breakpoint) +static int xscale_remove_breakpoint(struct target *target, struct breakpoint *breakpoint) { struct xscale_common *xscale = target_to_xscale(target); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_ERROR("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2225,22 +2292,20 @@ static int xscale_remove_breakpoint(struct target_s *target, struct breakpoint * return ERROR_OK; } -static int xscale_set_watchpoint(struct target_s *target, +static int xscale_set_watchpoint(struct target *target, struct watchpoint *watchpoint) { struct xscale_common *xscale = target_to_xscale(target); - uint8_t enable = 0; - reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON]; + uint32_t enable = 0; + struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON]; uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_ERROR("target not halted"); return ERROR_TARGET_NOT_HALTED; } - xscale_get_reg(dbcon); - switch (watchpoint->rw) { case WPT_READ: @@ -2256,6 +2321,24 @@ static int xscale_set_watchpoint(struct target_s *target, LOG_ERROR("BUG: watchpoint->rw neither read, write nor access"); } + /* For watchpoint across more than one word, both DBR registers must + be enlisted, with the second used as a mask. */ + if (watchpoint->length > 4) + { + if (xscale->dbr0_used || xscale->dbr1_used) + { + LOG_ERROR("BUG: sufficient hardware comparators unavailable"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + + /* Write mask value to DBR1, based on the length argument. + * Address bits ignored by the comparator are those set in mask. */ + xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR1], + watchpoint->length - 1); + xscale->dbr1_used = 1; + enable |= 0x100; /* DBCON[M] */ + } + if (!xscale->dbr0_used) { xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR0], watchpoint->address); @@ -2275,43 +2358,65 @@ static int xscale_set_watchpoint(struct target_s *target, else { LOG_ERROR("BUG: no hardware comparator available"); - return ERROR_OK; + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } return ERROR_OK; } -static int xscale_add_watchpoint(struct target_s *target, +static int xscale_add_watchpoint(struct target *target, struct watchpoint *watchpoint) { struct xscale_common *xscale = target_to_xscale(target); - if (target->state != TARGET_HALTED) + if (xscale->dbr_available < 1) { - LOG_WARNING("target not halted"); - return ERROR_TARGET_NOT_HALTED; + LOG_ERROR("no more watchpoint registers available"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } - if (xscale->dbr_available < 1) + if (watchpoint->value) + LOG_WARNING("xscale does not support value, mask arguments; ignoring"); + + /* check that length is a power of two */ + for (uint32_t len = watchpoint->length; len != 1; len /= 2) { - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + if (len % 2) + { + LOG_ERROR("xscale requires that watchpoint length is a power of two"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } } - if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4)) + if (watchpoint->length == 4) /* single word watchpoint */ { - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + xscale->dbr_available--; /* one DBR reg used */ + return ERROR_OK; } - xscale->dbr_available--; - + /* watchpoints across multiple words require both DBR registers */ + if (xscale->dbr_available < 2) + { + LOG_ERROR("insufficient watchpoint registers available"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + + if (watchpoint->length > watchpoint->address) + { + LOG_ERROR("xscale does not support watchpoints with length " + "greater than address"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + + xscale->dbr_available = 0; return ERROR_OK; } -static int xscale_unset_watchpoint(struct target_s *target, +static int xscale_unset_watchpoint(struct target *target, struct watchpoint *watchpoint) { struct xscale_common *xscale = target_to_xscale(target); - reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON]; + struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON]; uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32); if (target->state != TARGET_HALTED) @@ -2328,7 +2433,14 @@ static int xscale_unset_watchpoint(struct target_s *target, if (watchpoint->set == 1) { - dbcon_value &= ~0x3; + if (watchpoint->length > 4) + { + dbcon_value &= ~0x103; /* clear DBCON[M] as well */ + xscale->dbr1_used = 0; /* DBR1 was used for mask */ + } + else + dbcon_value &= ~0x3; + xscale_set_reg_u32(dbcon, dbcon_value); xscale->dbr0_used = 0; } @@ -2343,13 +2455,13 @@ static int xscale_unset_watchpoint(struct target_s *target, return ERROR_OK; } -static int xscale_remove_watchpoint(struct target_s *target, struct watchpoint *watchpoint) +static int xscale_remove_watchpoint(struct target *target, struct watchpoint *watchpoint) { struct xscale_common *xscale = target_to_xscale(target); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_ERROR("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2358,15 +2470,18 @@ static int xscale_remove_watchpoint(struct target_s *target, struct watchpoint * xscale_unset_watchpoint(target, watchpoint); } + if (watchpoint->length > 4) + xscale->dbr_available++; /* both DBR regs now available */ + xscale->dbr_available++; return ERROR_OK; } -static int xscale_get_reg(reg_t *reg) +static int xscale_get_reg(struct reg *reg) { struct xscale_reg *arch_info = reg->arch_info; - target_t *target = arch_info->target; + struct target *target = arch_info->target; struct xscale_common *xscale = target_to_xscale(target); /* DCSR, TX and RX are accessible via JTAG */ @@ -2408,10 +2523,10 @@ static int xscale_get_reg(reg_t *reg) return ERROR_OK; } -static int xscale_set_reg(reg_t *reg, uint8_t* buf) +static int xscale_set_reg(struct reg *reg, uint8_t* buf) { struct xscale_reg *arch_info = reg->arch_info; - target_t *target = arch_info->target; + struct target *target = arch_info->target; struct xscale_common *xscale = target_to_xscale(target); uint32_t value = buf_get_u32(buf, 0, 32); @@ -2452,10 +2567,10 @@ static int xscale_set_reg(reg_t *reg, uint8_t* buf) return ERROR_OK; } -static int xscale_write_dcsr_sw(target_t *target, uint32_t value) +static int xscale_write_dcsr_sw(struct target *target, uint32_t value) { struct xscale_common *xscale = target_to_xscale(target); - reg_t *dcsr = &xscale->reg_cache->reg_list[XSCALE_DCSR]; + struct reg *dcsr = &xscale->reg_cache->reg_list[XSCALE_DCSR]; struct xscale_reg *dcsr_arch_info = dcsr->arch_info; /* send CP write request (command 0x41) */ @@ -2471,10 +2586,10 @@ static int xscale_write_dcsr_sw(target_t *target, uint32_t value) return ERROR_OK; } -static int xscale_read_trace(target_t *target) +static int xscale_read_trace(struct target *target) { struct xscale_common *xscale = target_to_xscale(target); - struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common; + struct arm *armv4_5 = &xscale->armv4_5_common; struct xscale_trace_data **trace_data_p; /* 258 words from debug handler @@ -2484,6 +2599,7 @@ static int xscale_read_trace(target_t *target) uint32_t trace_buffer[258]; int is_address[256]; int i, j; + unsigned int num_checkpoints = 0; if (target->state != TARGET_HALTED) { @@ -2500,23 +2616,27 @@ static int xscale_read_trace(target_t *target) /* parse buffer backwards to identify address entries */ for (i = 255; i >= 0; i--) { + /* also count number of checkpointed entries */ + if ((trace_buffer[i] & 0xe0) == 0xc0) + num_checkpoints++; + is_address[i] = 0; if (((trace_buffer[i] & 0xf0) == 0x90) || ((trace_buffer[i] & 0xf0) == 0xd0)) { - if (i >= 3) + if (i > 0) is_address[--i] = 1; - if (i >= 2) + if (i > 0) is_address[--i] = 1; - if (i >= 1) + if (i > 0) is_address[--i] = 1; - if (i >= 0) + if (i > 0) is_address[--i] = 1; } } - /* search first non-zero entry */ + /* search first non-zero entry that is not part of an address */ for (j = 0; (j < 256) && (trace_buffer[j] == 0) && (!is_address[j]); j++) ; @@ -2526,6 +2646,22 @@ static int xscale_read_trace(target_t *target) return ERROR_XSCALE_NO_TRACE_DATA; } + /* account for possible partial address at buffer start (wrap mode only) */ + if (is_address[0]) + { /* first entry is address; complete set of 4? */ + i = 1; + while (i < 4) + if (!is_address[i++]) + break; + if (i < 4) + j += i; /* partial address; can't use it */ + } + + /* if first valid entry is indirect branch, can't use that either (no address) */ + if (((trace_buffer[j] & 0xf0) == 0x90) || ((trace_buffer[j] & 0xf0) == 0xd0)) + j++; + + /* walk linked list to terminating entry */ for (trace_data_p = &xscale->trace.data; *trace_data_p; trace_data_p = &(*trace_data_p)->next) ; @@ -2533,9 +2669,11 @@ static int xscale_read_trace(target_t *target) (*trace_data_p)->next = NULL; (*trace_data_p)->chkpt0 = trace_buffer[256]; (*trace_data_p)->chkpt1 = trace_buffer[257]; - (*trace_data_p)->last_instruction = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); + (*trace_data_p)->last_instruction = + buf_get_u32(armv4_5->pc->value, 0, 32); (*trace_data_p)->entries = malloc(sizeof(struct xscale_trace_entry) * (256 - j)); (*trace_data_p)->depth = 256 - j; + (*trace_data_p)->num_checkpoints = num_checkpoints; for (i = j; i < 256; i++) { @@ -2549,13 +2687,13 @@ static int xscale_read_trace(target_t *target) return ERROR_OK; } -static int xscale_read_instruction(target_t *target, - struct arm_instruction *instruction) +static int xscale_read_instruction(struct target *target, uint32_t pc, + struct arm_instruction *instruction) { - struct xscale_common *xscale = target_to_xscale(target); + struct xscale_common *const xscale = target_to_xscale(target); int i; int section = -1; - uint32_t size_read; + size_t size_read; uint32_t opcode; int retval; @@ -2565,8 +2703,8 @@ static int xscale_read_instruction(target_t *target, /* search for the section the current instruction belongs to */ for (i = 0; i < xscale->trace.image->num_sections; i++) { - if ((xscale->trace.image->sections[i].base_address <= xscale->trace.current_pc) && - (xscale->trace.image->sections[i].base_address + xscale->trace.image->sections[i].size > xscale->trace.current_pc)) + if ((xscale->trace.image->sections[i].base_address <= pc) && + (xscale->trace.image->sections[i].base_address + xscale->trace.image->sections[i].size > pc)) { section = i; break; @@ -2579,31 +2717,31 @@ static int xscale_read_instruction(target_t *target, return ERROR_TRACE_INSTRUCTION_UNAVAILABLE; } - if (xscale->trace.core_state == ARMV4_5_STATE_ARM) + if (xscale->trace.core_state == ARM_STATE_ARM) { uint8_t buf[4]; if ((retval = image_read_section(xscale->trace.image, section, - xscale->trace.current_pc - xscale->trace.image->sections[section].base_address, + pc - xscale->trace.image->sections[section].base_address, 4, buf, &size_read)) != ERROR_OK) { LOG_ERROR("error while reading instruction: %i", retval); return ERROR_TRACE_INSTRUCTION_UNAVAILABLE; } opcode = target_buffer_get_u32(target, buf); - arm_evaluate_opcode(opcode, xscale->trace.current_pc, instruction); + arm_evaluate_opcode(opcode, pc, instruction); } - else if (xscale->trace.core_state == ARMV4_5_STATE_THUMB) + else if (xscale->trace.core_state == ARM_STATE_THUMB) { uint8_t buf[2]; if ((retval = image_read_section(xscale->trace.image, section, - xscale->trace.current_pc - xscale->trace.image->sections[section].base_address, + pc - xscale->trace.image->sections[section].base_address, 2, buf, &size_read)) != ERROR_OK) { LOG_ERROR("error while reading instruction: %i", retval); return ERROR_TRACE_INSTRUCTION_UNAVAILABLE; } opcode = target_buffer_get_u16(target, buf); - thumb_evaluate_opcode(opcode, xscale->trace.current_pc, instruction); + thumb_evaluate_opcode(opcode, pc, instruction); } else { @@ -2614,224 +2752,251 @@ static int xscale_read_instruction(target_t *target, return ERROR_OK; } -static int xscale_branch_address(struct xscale_trace_data *trace_data, - int i, uint32_t *target) +/* Extract address encoded into trace data. + * Write result to address referenced by argument 'target', or 0 if incomplete. */ +static inline void xscale_branch_address(struct xscale_trace_data *trace_data, + int i, uint32_t *target) { /* if there are less than four entries prior to the indirect branch message * we can't extract the address */ if (i < 4) - { - return -1; - } - - *target = (trace_data->entries[i-1].data) | (trace_data->entries[i-2].data << 8) | - (trace_data->entries[i-3].data << 16) | (trace_data->entries[i-4].data << 24); - - return 0; -} - -static int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx) -{ - struct xscale_common *xscale = target_to_xscale(target); - int next_pc_ok = 0; - uint32_t next_pc = 0x0; - struct xscale_trace_data *trace_data = xscale->trace.data; - int retval; + *target = 0; + else + *target = (trace_data->entries[i-1].data) | (trace_data->entries[i-2].data << 8) | + (trace_data->entries[i-3].data << 16) | (trace_data->entries[i-4].data << 24); +} + +static inline void xscale_display_instruction(struct target *target, uint32_t pc, + struct arm_instruction *instruction, + struct command_context *cmd_ctx) +{ + int retval = xscale_read_instruction(target, pc, instruction); + if (retval == ERROR_OK) + command_print(cmd_ctx, "%s", instruction->text); + else + command_print(cmd_ctx, "0x%8.8" PRIx32 "\t", pc); +} + +static int xscale_analyze_trace(struct target *target, struct command_context *cmd_ctx) +{ + struct xscale_common *xscale = target_to_xscale(target); + struct xscale_trace_data *trace_data = xscale->trace.data; + int i, retval; + uint32_t breakpoint_pc; + struct arm_instruction instruction; + uint32_t current_pc = 0; /* initialized when address determined */ + + if (!xscale->trace.image) + LOG_WARNING("No trace image loaded; use 'xscale trace_image'"); + + /* loop for each trace buffer that was loaded from target */ + while (trace_data) + { + int chkpt = 0; /* incremented as checkpointed entries found */ + int j; + + /* FIXME: set this to correct mode when trace buffer is first enabled */ + xscale->trace.core_state = ARM_STATE_ARM; + + /* loop for each entry in this trace buffer */ + for (i = 0; i < trace_data->depth; i++) + { + int exception = 0; + uint32_t chkpt_reg = 0x0; + uint32_t branch_target = 0; + int count; + + /* trace entry type is upper nybble of 'message byte' */ + int trace_msg_type = (trace_data->entries[i].data & 0xf0) >> 4; + + /* Target addresses of indirect branches are written into buffer + * before the message byte representing the branch. Skip past it */ + if (trace_data->entries[i].type == XSCALE_TRACE_ADDRESS) + continue; + + switch (trace_msg_type) + { + case 0: /* Exceptions */ + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + exception = (trace_data->entries[i].data & 0x70) >> 4; + + /* FIXME: vector table may be at ffff0000 */ + branch_target = (trace_data->entries[i].data & 0xf0) >> 2; + break; + + case 8: /* Direct Branch */ + break; + + case 9: /* Indirect Branch */ + xscale_branch_address(trace_data, i, &branch_target); + break; + + case 13: /* Checkpointed Indirect Branch */ + xscale_branch_address(trace_data, i, &branch_target); + if ((trace_data->num_checkpoints == 2) && (chkpt == 0)) + chkpt_reg = trace_data->chkpt1; /* 2 chkpts, this is oldest */ + else + chkpt_reg = trace_data->chkpt0; /* 1 chkpt, or 2 and newest */ + + chkpt++; + break; + + case 12: /* Checkpointed Direct Branch */ + if ((trace_data->num_checkpoints == 2) && (chkpt == 0)) + chkpt_reg = trace_data->chkpt1; /* 2 chkpts, this is oldest */ + else + chkpt_reg = trace_data->chkpt0; /* 1 chkpt, or 2 and newest */ + + /* if no current_pc, checkpoint will be starting point */ + if (current_pc == 0) + branch_target = chkpt_reg; + + chkpt++; + break; + + case 15: /* Roll-over */ + break; + + default: /* Reserved */ + LOG_WARNING("trace is suspect: invalid trace message byte"); + continue; + + } + + /* If we don't have the current_pc yet, but we did get the branch target + * (either from the trace buffer on indirect branch, or from a checkpoint reg), + * then we can start displaying instructions at the next iteration, with + * branch_target as the starting point. + */ + if (current_pc == 0) + { + current_pc = branch_target; /* remains 0 unless branch_target obtained */ + continue; + } + + /* We have current_pc. Read and display the instructions from the image. + * First, display count instructions (lower nybble of message byte). */ + count = trace_data->entries[i].data & 0x0f; + for (j = 0; j < count; j++) + { + xscale_display_instruction(target, current_pc, &instruction, cmd_ctx); + current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2; + } + + /* An additional instruction is implicitly added to count for + * rollover and some exceptions: undef, swi, prefetch abort. */ + if ((trace_msg_type == 15) || (exception > 0 && exception < 4)) + { + xscale_display_instruction(target, current_pc, &instruction, cmd_ctx); + current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2; + } + + if (trace_msg_type == 15) /* rollover */ + continue; + + if (exception) + { + command_print(cmd_ctx, "--- exception %i ---", exception); + continue; + } + + /* not exception or rollover; next instruction is a branch and is + * not included in the count */ + xscale_display_instruction(target, current_pc, &instruction, cmd_ctx); + + /* for direct branches, extract branch destination from instruction */ + if ((trace_msg_type == 8) || (trace_msg_type == 12)) + { + retval = xscale_read_instruction(target, current_pc, &instruction); + if (retval == ERROR_OK) + current_pc = instruction.info.b_bl_bx_blx.target_address; + else + current_pc = 0; /* branch destination unknown */ - while (trace_data) - { - int i, chkpt; - int rollover; - int branch; - int exception; - xscale->trace.core_state = ARMV4_5_STATE_ARM; + /* direct branch w/ checkpoint; can also get from checkpoint reg */ + if (trace_msg_type == 12) + { + if (current_pc == 0) + current_pc = chkpt_reg; + else if (current_pc != chkpt_reg) /* sanity check */ + LOG_WARNING("trace is suspect: checkpoint register " + "inconsistent with adddress from image"); + } - chkpt = 0; - rollover = 0; + if (current_pc == 0) + command_print(cmd_ctx, "address unknown"); - for (i = 0; i < trace_data->depth; i++) - { - next_pc_ok = 0; - branch = 0; - exception = 0; + continue; + } - if (trace_data->entries[i].type == XSCALE_TRACE_ADDRESS) - continue; + /* indirect branch; the branch destination was read from trace buffer */ + if ((trace_msg_type == 9) || (trace_msg_type == 13)) + { + current_pc = branch_target; - switch ((trace_data->entries[i].data & 0xf0) >> 4) - { - case 0: /* Exceptions */ - case 1: - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: - exception = (trace_data->entries[i].data & 0x70) >> 4; - next_pc_ok = 1; - next_pc = (trace_data->entries[i].data & 0xf0) >> 2; - command_print(cmd_ctx, "--- exception %i ---", (trace_data->entries[i].data & 0xf0) >> 4); - break; - case 8: /* Direct Branch */ - branch = 1; - break; - case 9: /* Indirect Branch */ - branch = 1; - if (xscale_branch_address(trace_data, i, &next_pc) == 0) - { - next_pc_ok = 1; - } - break; - case 13: /* Checkpointed Indirect Branch */ - if (xscale_branch_address(trace_data, i, &next_pc) == 0) - { - next_pc_ok = 1; - if (((chkpt == 0) && (next_pc != trace_data->chkpt0)) - || ((chkpt == 1) && (next_pc != trace_data->chkpt1))) - LOG_WARNING("checkpointed indirect branch target address doesn't match checkpoint"); - } - /* explicit fall-through */ - case 12: /* Checkpointed Direct Branch */ - branch = 1; - if (chkpt == 0) - { - next_pc_ok = 1; - next_pc = trace_data->chkpt0; - chkpt++; - } - else if (chkpt == 1) - { - next_pc_ok = 1; - next_pc = trace_data->chkpt0; - chkpt++; - } - else - { - LOG_WARNING("more than two checkpointed branches encountered"); - } - break; - case 15: /* Roll-over */ - rollover++; - continue; - default: /* Reserved */ - command_print(cmd_ctx, "--- reserved trace message ---"); - LOG_ERROR("BUG: trace message %i is reserved", (trace_data->entries[i].data & 0xf0) >> 4); - return ERROR_OK; - } + /* sanity check (checkpoint reg is redundant) */ + if ((trace_msg_type == 13) && (chkpt_reg != branch_target)) + LOG_WARNING("trace is suspect: checkpoint register " + "inconsistent with address from trace buffer"); + } - if (xscale->trace.pc_ok) - { - int executed = (trace_data->entries[i].data & 0xf) + rollover * 16; - struct arm_instruction instruction; + } /* END: for (i = 0; i < trace_data->depth; i++) */ - if ((exception == 6) || (exception == 7)) - { - /* IRQ or FIQ exception, no instruction executed */ - executed -= 1; - } + breakpoint_pc = trace_data->last_instruction; /* used below */ + trace_data = trace_data->next; - while (executed-- >= 0) - { - if ((retval = xscale_read_instruction(target, &instruction)) != ERROR_OK) - { - /* can't continue tracing with no image available */ - if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE) - { - return retval; - } - else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE) - { - /* TODO: handle incomplete images */ - } - } - - /* a precise abort on a load to the PC is included in the incremental - * word count, other instructions causing data aborts are not included - */ - if ((executed == 0) && (exception == 4) - && ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDM))) - { - if ((instruction.type == ARM_LDM) - && ((instruction.info.load_store_multiple.register_list & 0x8000) == 0)) - { - executed--; - } - else if (((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDRSH)) - && (instruction.info.load_store.Rd != 15)) - { - executed--; - } - } - - /* only the last instruction executed - * (the one that caused the control flow change) - * could be a taken branch - */ - if (((executed == -1) && (branch == 1)) && - (((instruction.type == ARM_B) || - (instruction.type == ARM_BL) || - (instruction.type == ARM_BLX)) && - (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))) - { - xscale->trace.current_pc = instruction.info.b_bl_bx_blx.target_address; - } - else - { - xscale->trace.current_pc += (xscale->trace.core_state == ARMV4_5_STATE_ARM) ? 4 : 2; - } - command_print(cmd_ctx, "%s", instruction.text); - } + } /* END: while (trace_data) */ - rollover = 0; - } + /* Finally... display all instructions up to the value of the pc when the + * debug break occurred (saved when trace data was collected from target). + * This is necessary because the trace only records execution branches and 16 + * consecutive instructions (rollovers), so last few typically missed. + */ + if (current_pc == 0) + return ERROR_OK; /* current_pc was never found */ - if (next_pc_ok) - { - xscale->trace.current_pc = next_pc; - xscale->trace.pc_ok = 1; - } - } + /* how many instructions remaining? */ + int gap_count = (breakpoint_pc - current_pc) / + (xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2); - for (; xscale->trace.current_pc < trace_data->last_instruction; xscale->trace.current_pc += (xscale->trace.core_state == ARMV4_5_STATE_ARM) ? 4 : 2) - { - struct arm_instruction instruction; - if ((retval = xscale_read_instruction(target, &instruction)) != ERROR_OK) - { - /* can't continue tracing with no image available */ - if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE) - { - return retval; - } - else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE) - { - /* TODO: handle incomplete images */ - } - } - command_print(cmd_ctx, "%s", instruction.text); - } + /* should never be negative or over 16, but verify */ + if (gap_count < 0 || gap_count > 16) + { + LOG_WARNING("trace is suspect: excessive gap at end of trace"); + return ERROR_OK; /* bail; large number or negative value no good */ + } - trace_data = trace_data->next; - } + /* display remaining instructions */ + for (i = 0; i < gap_count; i++) + { + xscale_display_instruction(target, current_pc, &instruction, cmd_ctx); + current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2; + } - return ERROR_OK; + return ERROR_OK; } -static void xscale_build_reg_cache(target_t *target) +static const struct reg_arch_type xscale_reg_type = { + .get = xscale_get_reg, + .set = xscale_set_reg, +}; + +static void xscale_build_reg_cache(struct target *target) { struct xscale_common *xscale = target_to_xscale(target); - struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common; + struct arm *armv4_5 = &xscale->armv4_5_common; struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); struct xscale_reg *arch_info = malloc(sizeof(xscale_reg_arch_info)); int i; - int num_regs = sizeof(xscale_reg_arch_info) / sizeof(struct xscale_reg); - - (*cache_p) = armv4_5_build_reg_cache(target, armv4_5); - armv4_5->core_cache = (*cache_p); + int num_regs = ARRAY_SIZE(xscale_reg_arch_info); - /* register a register arch-type for XScale dbg registers only once */ - if (xscale_reg_arch_type == -1) - xscale_reg_arch_type = register_reg_arch_type(xscale_get_reg, xscale_set_reg); + (*cache_p) = arm_build_reg_cache(target, armv4_5); (*cache_p)->next = malloc(sizeof(struct reg_cache)); cache_p = &(*cache_p)->next; @@ -2839,7 +3004,7 @@ static void xscale_build_reg_cache(target_t *target) /* fill in values for the xscale reg cache */ (*cache_p)->name = "XScale registers"; (*cache_p)->next = NULL; - (*cache_p)->reg_list = malloc(num_regs * sizeof(reg_t)); + (*cache_p)->reg_list = malloc(num_regs * sizeof(struct reg)); (*cache_p)->num_regs = num_regs; for (i = 0; i < num_regs; i++) @@ -2849,10 +3014,8 @@ static void xscale_build_reg_cache(target_t *target) (*cache_p)->reg_list[i].dirty = 0; (*cache_p)->reg_list[i].valid = 0; (*cache_p)->reg_list[i].size = 32; - (*cache_p)->reg_list[i].bitfield_desc = NULL; - (*cache_p)->reg_list[i].num_bitfields = 0; (*cache_p)->reg_list[i].arch_info = &arch_info[i]; - (*cache_p)->reg_list[i].arch_type = xscale_reg_arch_type; + (*cache_p)->reg_list[i].type = &xscale_reg_type; arch_info[i] = xscale_reg_arch_info[i]; arch_info[i].target = target; } @@ -2860,14 +3023,14 @@ static void xscale_build_reg_cache(target_t *target) xscale->reg_cache = (*cache_p); } -static int xscale_init_target(struct command_context_s *cmd_ctx, - struct target_s *target) +static int xscale_init_target(struct command_context *cmd_ctx, + struct target *target) { xscale_build_reg_cache(target); return ERROR_OK; } -static int xscale_init_arch_info(target_t *target, +static int xscale_init_arch_info(struct target *target, struct xscale_common *xscale, struct jtag_tap *tap, const char *variant) { struct arm *armv4_5; @@ -2876,10 +3039,10 @@ static int xscale_init_arch_info(target_t *target, armv4_5 = &xscale->armv4_5_common; - /* store architecture specfic data (none so far) */ + /* store architecture specfic data */ xscale->common_magic = XSCALE_COMMON_MAGIC; - /* we don't really *need* variant info ... */ + /* we don't really *need* a variant param ... */ if (variant) { int ir_length = 0; @@ -2892,6 +3055,8 @@ static int xscale_init_arch_info(target_t *target, || strcmp(variant, "ixp45x") == 0 || strcmp(variant, "ixp46x") == 0) ir_length = 7; + else if (strcmp(variant, "pxa3xx") == 0) + ir_length = 11; else LOG_WARNING("%s: unrecognized variant %s", tap->dotted_name, variant); @@ -2903,6 +3068,12 @@ static int xscale_init_arch_info(target_t *target, } } + /* PXA3xx shifts the JTAG instructions */ + if (tap->ir_length == 11) + xscale->xscale_variant = XSCALE_PXA3XX; + else + xscale->xscale_variant = XSCALE_IXP4XX_PXA2XX; + /* the debug handler isn't installed (and thus not running) at this time */ xscale->handler_address = 0xfe000800; @@ -2941,6 +3112,9 @@ static int xscale_init_arch_info(target_t *target, xscale->dbr0_used = 0; xscale->dbr1_used = 0; + LOG_INFO("%s: hardware has 2 breakpoints and 2 watchpoints", + target_name(target)); + xscale->arm_bkpt = ARMV5_BKPT(0x0); xscale->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff; @@ -2958,7 +3132,7 @@ static int xscale_init_arch_info(target_t *target, armv4_5->write_core_reg = xscale_write_core_reg; armv4_5->full_context = xscale_full_context; - armv4_5_init_arch_info(target, armv4_5); + arm_init_arch_info(target, armv4_5); xscale->armv4_5_mmu.armv4_5_cache.ctype = -1; xscale->armv4_5_mmu.get_ttb = xscale_get_ttb; @@ -2972,7 +3146,7 @@ static int xscale_init_arch_info(target_t *target, return ERROR_OK; } -static int xscale_target_create(struct target_s *target, Jim_Interp *interp) +static int xscale_target_create(struct target *target, Jim_Interp *interp) { struct xscale_common *xscale; @@ -2991,29 +3165,29 @@ static int xscale_target_create(struct target_s *target, Jim_Interp *interp) COMMAND_HANDLER(xscale_handle_debug_handler_command) { - target_t *target = NULL; + struct target *target = NULL; struct xscale_common *xscale; int retval; uint32_t handler_address; - if (argc < 2) + if (CMD_ARGC < 2) { LOG_ERROR("'xscale debug_handler
' command takes two required operands"); return ERROR_OK; } - if ((target = get_target(args[0])) == NULL) + if ((target = get_target(CMD_ARGV[0])) == NULL) { - LOG_ERROR("target '%s' not defined", args[0]); + LOG_ERROR("target '%s' not defined", CMD_ARGV[0]); return ERROR_FAIL; } xscale = target_to_xscale(target); - retval = xscale_verify_pointer(cmd_ctx, xscale); + retval = xscale_verify_pointer(CMD_CTX, xscale); if (retval != ERROR_OK) return retval; - COMMAND_PARSE_NUMBER(u32, args[1], handler_address); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], handler_address); if (((handler_address >= 0x800) && (handler_address <= 0x1fef800)) || ((handler_address >= 0xfe000800) && (handler_address <= 0xfffff800))) @@ -3031,28 +3205,28 @@ COMMAND_HANDLER(xscale_handle_debug_handler_command) COMMAND_HANDLER(xscale_handle_cache_clean_address_command) { - target_t *target = NULL; + struct target *target = NULL; struct xscale_common *xscale; int retval; uint32_t cache_clean_address; - if (argc < 2) + if (CMD_ARGC < 2) { return ERROR_COMMAND_SYNTAX_ERROR; } - target = get_target(args[0]); + target = get_target(CMD_ARGV[0]); if (target == NULL) { - LOG_ERROR("target '%s' not defined", args[0]); + LOG_ERROR("target '%s' not defined", CMD_ARGV[0]); return ERROR_FAIL; } xscale = target_to_xscale(target); - retval = xscale_verify_pointer(cmd_ctx, xscale); + retval = xscale_verify_pointer(CMD_CTX, xscale); if (retval != ERROR_OK) return retval; - COMMAND_PARSE_NUMBER(u32, args[1], cache_clean_address); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cache_clean_address); if (cache_clean_address & 0xffff) { @@ -3068,41 +3242,38 @@ COMMAND_HANDLER(xscale_handle_cache_clean_address_command) COMMAND_HANDLER(xscale_handle_cache_info_command) { - target_t *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct xscale_common *xscale = target_to_xscale(target); int retval; - retval = xscale_verify_pointer(cmd_ctx, xscale); + retval = xscale_verify_pointer(CMD_CTX, xscale); if (retval != ERROR_OK) return retval; - return armv4_5_handle_cache_info_command(cmd_ctx, &xscale->armv4_5_mmu.armv4_5_cache); + return armv4_5_handle_cache_info_command(CMD_CTX, &xscale->armv4_5_mmu.armv4_5_cache); } -static int xscale_virt2phys(struct target_s *target, +static int xscale_virt2phys(struct target *target, uint32_t virtual, uint32_t *physical) { struct xscale_common *xscale = target_to_xscale(target); - int type; uint32_t cb; - int domain; - uint32_t ap; if (xscale->common_magic != XSCALE_COMMON_MAGIC) { LOG_ERROR(xscale_not); return ERROR_TARGET_INVALID; } - uint32_t ret = armv4_5_mmu_translate_va(target, &xscale->armv4_5_mmu, virtual, &type, &cb, &domain, &ap); - if (type == -1) - { - return ret; - } + uint32_t ret; + int retval = armv4_5_mmu_translate_va(target, &xscale->armv4_5_mmu, + virtual, &cb, &ret); + if (retval != ERROR_OK) + return retval; *physical = ret; return ERROR_OK; } -static int xscale_mmu(struct target_s *target, int *enabled) +static int xscale_mmu(struct target *target, int *enabled) { struct xscale_common *xscale = target_to_xscale(target); @@ -3117,114 +3288,104 @@ static int xscale_mmu(struct target_s *target, int *enabled) COMMAND_HANDLER(xscale_handle_mmu_command) { - target_t *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct xscale_common *xscale = target_to_xscale(target); int retval; - retval = xscale_verify_pointer(cmd_ctx, xscale); + retval = xscale_verify_pointer(CMD_CTX, xscale); if (retval != ERROR_OK) return retval; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); + command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } - if (argc >= 1) + if (CMD_ARGC >= 1) { - if (strcmp("enable", args[0]) == 0) - { + bool enable; + COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable); + if (enable) xscale_enable_mmu_caches(target, 1, 0, 0); - xscale->armv4_5_mmu.mmu_enabled = 1; - } - else if (strcmp("disable", args[0]) == 0) - { + else xscale_disable_mmu_caches(target, 1, 0, 0); - xscale->armv4_5_mmu.mmu_enabled = 0; - } + xscale->armv4_5_mmu.mmu_enabled = enable; } - command_print(cmd_ctx, "mmu %s", (xscale->armv4_5_mmu.mmu_enabled) ? "enabled" : "disabled"); + command_print(CMD_CTX, "mmu %s", (xscale->armv4_5_mmu.mmu_enabled) ? "enabled" : "disabled"); return ERROR_OK; } COMMAND_HANDLER(xscale_handle_idcache_command) { - target_t *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct xscale_common *xscale = target_to_xscale(target); - int icache = 0, dcache = 0; - int retval; - retval = xscale_verify_pointer(cmd_ctx, xscale); + int retval = xscale_verify_pointer(CMD_CTX, xscale); if (retval != ERROR_OK) return retval; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); + command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } + bool icache = false; if (strcmp(CMD_NAME, "icache") == 0) - icache = 1; - else if (strcmp(CMD_NAME, "dcache") == 0) - dcache = 1; - - if (argc >= 1) - { - if (strcmp("enable", args[0]) == 0) - { - xscale_enable_mmu_caches(target, 0, dcache, icache); - - if (icache) - xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 1; - else if (dcache) - xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 1; - } - else if (strcmp("disable", args[0]) == 0) - { - xscale_disable_mmu_caches(target, 0, dcache, icache); - - if (icache) - xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0; - else if (dcache) - xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; + icache = true; + if (CMD_ARGC >= 1) + { + bool enable; + COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable); + if (icache) { + xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = enable; + if (enable) + xscale_enable_mmu_caches(target, 0, 0, 1); + else + xscale_disable_mmu_caches(target, 0, 0, 1); + } else { + xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = enable; + if (enable) + xscale_enable_mmu_caches(target, 0, 1, 0); + else + xscale_disable_mmu_caches(target, 0, 1, 0); } } - if (icache) - command_print(cmd_ctx, "icache %s", (xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled) ? "enabled" : "disabled"); - - if (dcache) - command_print(cmd_ctx, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled"); + bool enabled = icache ? + xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled : + xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled; + const char *msg = enabled ? "enabled" : "disabled"; + command_print(CMD_CTX, "%s %s", CMD_NAME, msg); return ERROR_OK; } COMMAND_HANDLER(xscale_handle_vector_catch_command) { - target_t *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct xscale_common *xscale = target_to_xscale(target); int retval; - retval = xscale_verify_pointer(cmd_ctx, xscale); + retval = xscale_verify_pointer(CMD_CTX, xscale); if (retval != ERROR_OK) return retval; - if (argc < 1) + if (CMD_ARGC < 1) { - command_print(cmd_ctx, "usage: xscale vector_catch [mask]"); + command_print(CMD_CTX, "usage: xscale vector_catch [mask]"); } else { - COMMAND_PARSE_NUMBER(u8, args[0], xscale->vector_catch); + COMMAND_PARSE_NUMBER(u8, CMD_ARGV[0], xscale->vector_catch); buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 8, xscale->vector_catch); xscale_write_dcsr(target, -1, -1); } - command_print(cmd_ctx, "vector catch mask: 0x%2.2x", xscale->vector_catch); + command_print(CMD_CTX, "vector catch mask: 0x%2.2x", xscale->vector_catch); return ERROR_OK; } @@ -3232,47 +3393,47 @@ COMMAND_HANDLER(xscale_handle_vector_catch_command) COMMAND_HANDLER(xscale_handle_vector_table_command) { - target_t *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct xscale_common *xscale = target_to_xscale(target); int err = 0; int retval; - retval = xscale_verify_pointer(cmd_ctx, xscale); + retval = xscale_verify_pointer(CMD_CTX, xscale); if (retval != ERROR_OK) return retval; - if (argc == 0) /* print current settings */ + if (CMD_ARGC == 0) /* print current settings */ { int idx; - command_print(cmd_ctx, "active user-set static vectors:"); + command_print(CMD_CTX, "active user-set static vectors:"); for (idx = 1; idx < 8; idx++) if (xscale->static_low_vectors_set & (1 << idx)) - command_print(cmd_ctx, "low %d: 0x%" PRIx32, idx, xscale->static_low_vectors[idx]); + command_print(CMD_CTX, "low %d: 0x%" PRIx32, idx, xscale->static_low_vectors[idx]); for (idx = 1; idx < 8; idx++) if (xscale->static_high_vectors_set & (1 << idx)) - command_print(cmd_ctx, "high %d: 0x%" PRIx32, idx, xscale->static_high_vectors[idx]); + command_print(CMD_CTX, "high %d: 0x%" PRIx32, idx, xscale->static_high_vectors[idx]); return ERROR_OK; } - if (argc != 3) + if (CMD_ARGC != 3) err = 1; else { int idx; - COMMAND_PARSE_NUMBER(int, args[1], idx); + COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], idx); uint32_t vec; - COMMAND_PARSE_NUMBER(u32, args[2], vec); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], vec); if (idx < 1 || idx >= 8) err = 1; - if (!err && strcmp(args[0], "low") == 0) + if (!err && strcmp(CMD_ARGV[0], "low") == 0) { xscale->static_low_vectors_set |= (1<static_low_vectors[idx] = vec; } - else if (!err && (strcmp(args[0], "high") == 0)) + else if (!err && (strcmp(CMD_ARGV[0], "high") == 0)) { xscale->static_high_vectors_set |= (1<static_high_vectors[idx] = vec; @@ -3282,7 +3443,7 @@ COMMAND_HANDLER(xscale_handle_vector_table_command) } if (err) - command_print(cmd_ctx, "usage: xscale vector_table "); + command_print(CMD_CTX, "usage: xscale vector_table "); return ERROR_OK; } @@ -3290,23 +3451,22 @@ COMMAND_HANDLER(xscale_handle_vector_table_command) COMMAND_HANDLER(xscale_handle_trace_buffer_command) { - target_t *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct xscale_common *xscale = target_to_xscale(target); - struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common; uint32_t dcsr_value; int retval; - retval = xscale_verify_pointer(cmd_ctx, xscale); + retval = xscale_verify_pointer(CMD_CTX, xscale); if (retval != ERROR_OK) return retval; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); + command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } - if ((argc >= 1) && (strcmp("enable", args[0]) == 0)) + if ((CMD_ARGC >= 1) && (strcmp("enable", CMD_ARGV[0]) == 0)) { struct xscale_trace_data *td, *next_td; xscale->trace.buffer_enabled = 1; @@ -3324,37 +3484,24 @@ COMMAND_HANDLER(xscale_handle_trace_buffer_command) } xscale->trace.data = NULL; } - else if ((argc >= 1) && (strcmp("disable", args[0]) == 0)) + else if ((CMD_ARGC >= 1) && (strcmp("disable", CMD_ARGV[0]) == 0)) { xscale->trace.buffer_enabled = 0; } - if ((argc >= 2) && (strcmp("fill", args[1]) == 0)) + if ((CMD_ARGC >= 2) && (strcmp("fill", CMD_ARGV[1]) == 0)) { uint32_t fill = 1; - if (argc >= 3) - COMMAND_PARSE_NUMBER(u32, args[2], fill); + if (CMD_ARGC >= 3) + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], fill); xscale->trace.buffer_fill = fill; } - else if ((argc >= 2) && (strcmp("wrap", args[1]) == 0)) + else if ((CMD_ARGC >= 2) && (strcmp("wrap", CMD_ARGV[1]) == 0)) { xscale->trace.buffer_fill = -1; } - if (xscale->trace.buffer_enabled) - { - /* if we enable the trace buffer in fill-once - * mode we know the address of the first instruction */ - xscale->trace.pc_ok = 1; - xscale->trace.current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); - } - else - { - /* otherwise the address is unknown, and we have no known good PC */ - xscale->trace.pc_ok = 0; - } - - command_print(cmd_ctx, "trace buffer %s (%s)", + command_print(CMD_CTX, "trace buffer %s (%s)", (xscale->trace.buffer_enabled) ? "enabled" : "disabled", (xscale->trace.buffer_fill > 0) ? "fill" : "wrap"); @@ -3369,17 +3516,17 @@ COMMAND_HANDLER(xscale_handle_trace_buffer_command) COMMAND_HANDLER(xscale_handle_trace_image_command) { - target_t *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct xscale_common *xscale = target_to_xscale(target); int retval; - if (argc < 1) + if (CMD_ARGC < 1) { - command_print(cmd_ctx, "usage: xscale trace_image [base address] [type]"); + command_print(CMD_CTX, "usage: xscale trace_image [base address] [type]"); return ERROR_OK; } - retval = xscale_verify_pointer(cmd_ctx, xscale); + retval = xscale_verify_pointer(CMD_CTX, xscale); if (retval != ERROR_OK) return retval; @@ -3387,25 +3534,25 @@ COMMAND_HANDLER(xscale_handle_trace_image_command) { image_close(xscale->trace.image); free(xscale->trace.image); - command_print(cmd_ctx, "previously loaded image found and closed"); + command_print(CMD_CTX, "previously loaded image found and closed"); } - xscale->trace.image = malloc(sizeof(image_t)); + xscale->trace.image = malloc(sizeof(struct image)); xscale->trace.image->base_address_set = 0; xscale->trace.image->start_address_set = 0; /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */ - if (argc >= 2) + if (CMD_ARGC >= 2) { xscale->trace.image->base_address_set = 1; - COMMAND_PARSE_NUMBER(int, args[1], xscale->trace.image->base_address); + COMMAND_PARSE_NUMBER(llong, CMD_ARGV[1], xscale->trace.image->base_address); } else { xscale->trace.image->base_address_set = 0; } - if (image_open(xscale->trace.image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK) + if (image_open(xscale->trace.image, CMD_ARGV[0], (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK) { free(xscale->trace.image); xscale->trace.image = NULL; @@ -3417,25 +3564,25 @@ COMMAND_HANDLER(xscale_handle_trace_image_command) COMMAND_HANDLER(xscale_handle_dump_trace_command) { - target_t *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct xscale_common *xscale = target_to_xscale(target); struct xscale_trace_data *trace_data; struct fileio file; int retval; - retval = xscale_verify_pointer(cmd_ctx, xscale); + retval = xscale_verify_pointer(CMD_CTX, xscale); if (retval != ERROR_OK) return retval; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); + command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } - if (argc < 1) + if (CMD_ARGC < 1) { - command_print(cmd_ctx, "usage: xscale dump_trace "); + command_print(CMD_CTX, "usage: xscale dump_trace "); return ERROR_OK; } @@ -3443,11 +3590,11 @@ COMMAND_HANDLER(xscale_handle_dump_trace_command) if (!trace_data) { - command_print(cmd_ctx, "no trace data collected"); + command_print(CMD_CTX, "no trace data collected"); return ERROR_OK; } - if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK) + if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK) { return ERROR_OK; } @@ -3474,39 +3621,39 @@ COMMAND_HANDLER(xscale_handle_dump_trace_command) COMMAND_HANDLER(xscale_handle_analyze_trace_buffer_command) { - target_t *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct xscale_common *xscale = target_to_xscale(target); int retval; - retval = xscale_verify_pointer(cmd_ctx, xscale); + retval = xscale_verify_pointer(CMD_CTX, xscale); if (retval != ERROR_OK) return retval; - xscale_analyze_trace(target, cmd_ctx); + xscale_analyze_trace(target, CMD_CTX); return ERROR_OK; } COMMAND_HANDLER(xscale_handle_cp15) { - target_t *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct xscale_common *xscale = target_to_xscale(target); int retval; - retval = xscale_verify_pointer(cmd_ctx, xscale); + retval = xscale_verify_pointer(CMD_CTX, xscale); if (retval != ERROR_OK) return retval; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); + command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } uint32_t reg_no = 0; - reg_t *reg = NULL; - if (argc > 0) + struct reg *reg = NULL; + if (CMD_ARGC > 0) { - COMMAND_PARSE_NUMBER(u32, args[0], reg_no); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], reg_no); /*translate from xscale cp15 register no to openocd register*/ switch (reg_no) { @@ -3535,25 +3682,25 @@ COMMAND_HANDLER(xscale_handle_cp15) reg_no = XSCALE_CPACCESS; break; default: - command_print(cmd_ctx, "invalid register number"); + command_print(CMD_CTX, "invalid register number"); return ERROR_INVALID_ARGUMENTS; } reg = &xscale->reg_cache->reg_list[reg_no]; } - if (argc == 1) + if (CMD_ARGC == 1) { uint32_t value; /* read cp15 control register */ xscale_get_reg(reg); value = buf_get_u32(reg->value, 0, 32); - command_print(cmd_ctx, "%s (/%i): 0x%" PRIx32 "", reg->name, (int)(reg->size), value); + command_print(CMD_CTX, "%s (/%i): 0x%" PRIx32 "", reg->name, (int)(reg->size), value); } - else if (argc == 2) + else if (CMD_ARGC == 2) { uint32_t value; - COMMAND_PARSE_NUMBER(u32, args[1], value); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); /* send CP write request (command 0x41) */ xscale_send_u32(target, 0x41); @@ -3569,44 +3716,130 @@ COMMAND_HANDLER(xscale_handle_cp15) } else { - command_print(cmd_ctx, "usage: cp15 [register]<, [value]>"); + command_print(CMD_CTX, "usage: cp15 [register]<, [value]>"); } return ERROR_OK; } -static int xscale_register_commands(struct command_context_s *cmd_ctx) -{ - command_t *xscale_cmd; - - xscale_cmd = register_command(cmd_ctx, NULL, "xscale", NULL, COMMAND_ANY, "xscale specific commands"); - - register_command(cmd_ctx, xscale_cmd, "debug_handler", xscale_handle_debug_handler_command, COMMAND_ANY, "'xscale debug_handler
' command takes two required operands"); - register_command(cmd_ctx, xscale_cmd, "cache_clean_address", xscale_handle_cache_clean_address_command, COMMAND_ANY, NULL); - - register_command(cmd_ctx, xscale_cmd, "cache_info", xscale_handle_cache_info_command, COMMAND_EXEC, NULL); - register_command(cmd_ctx, xscale_cmd, "mmu", xscale_handle_mmu_command, COMMAND_EXEC, "['enable'|'disable'] the MMU"); - register_command(cmd_ctx, xscale_cmd, "icache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the ICache"); - register_command(cmd_ctx, xscale_cmd, "dcache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the DCache"); - - register_command(cmd_ctx, xscale_cmd, "vector_catch", xscale_handle_vector_catch_command, COMMAND_EXEC, " of vectors that should be catched"); - register_command(cmd_ctx, xscale_cmd, "vector_table", xscale_handle_vector_table_command, COMMAND_EXEC, " set static code for exception handler entry"); - - register_command(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, " ['fill' [n]|'wrap']"); - - register_command(cmd_ctx, xscale_cmd, "dump_trace", xscale_handle_dump_trace_command, COMMAND_EXEC, "dump content of trace buffer to "); - register_command(cmd_ctx, xscale_cmd, "analyze_trace", xscale_handle_analyze_trace_buffer_command, COMMAND_EXEC, "analyze content of trace buffer"); - register_command(cmd_ctx, xscale_cmd, "trace_image", xscale_handle_trace_image_command, - COMMAND_EXEC, "load image from [base address]"); - - register_command(cmd_ctx, xscale_cmd, "cp15", xscale_handle_cp15, COMMAND_EXEC, "access coproc 15 [value]"); - - armv4_5_register_commands(cmd_ctx); - - return ERROR_OK; -} +static const struct command_registration xscale_exec_command_handlers[] = { + { + .name = "cache_info", + .handler = xscale_handle_cache_info_command, + .mode = COMMAND_EXEC, + .help = "display information about CPU caches", + }, + { + .name = "mmu", + .handler = xscale_handle_mmu_command, + .mode = COMMAND_EXEC, + .help = "enable or disable the MMU", + .usage = "['enable'|'disable']", + }, + { + .name = "icache", + .handler = xscale_handle_idcache_command, + .mode = COMMAND_EXEC, + .help = "display ICache state, optionally enabling or " + "disabling it", + .usage = "['enable'|'disable']", + }, + { + .name = "dcache", + .handler = xscale_handle_idcache_command, + .mode = COMMAND_EXEC, + .help = "display DCache state, optionally enabling or " + "disabling it", + .usage = "['enable'|'disable']", + }, + { + .name = "vector_catch", + .handler = xscale_handle_vector_catch_command, + .mode = COMMAND_EXEC, + .help = "set or display 8-bit mask of vectors " + "that should trigger debug entry", + .usage = "[mask]", + }, + { + .name = "vector_table", + .handler = xscale_handle_vector_table_command, + .mode = COMMAND_EXEC, + .help = "set vector table entry in mini-ICache, " + "or display current tables", + .usage = "[('high'|'low') index code]", + }, + { + .name = "trace_buffer", + .handler = xscale_handle_trace_buffer_command, + .mode = COMMAND_EXEC, + .help = "display trace buffer status, enable or disable " + "tracing, and optionally reconfigure trace mode", + .usage = "['enable'|'disable' ['fill' number|'wrap']]", + }, + { + .name = "dump_trace", + .handler = xscale_handle_dump_trace_command, + .mode = COMMAND_EXEC, + .help = "dump content of trace buffer to file", + .usage = "filename", + }, + { + .name = "analyze_trace", + .handler = xscale_handle_analyze_trace_buffer_command, + .mode = COMMAND_EXEC, + .help = "analyze content of trace buffer", + .usage = "", + }, + { + .name = "trace_image", + .handler = xscale_handle_trace_image_command, + .mode = COMMAND_EXEC, + .help = "load image from file to address (default 0)", + .usage = "filename [offset [filetype]]", + }, + { + .name = "cp15", + .handler = xscale_handle_cp15, + .mode = COMMAND_EXEC, + .help = "Read or write coprocessor 15 register.", + .usage = "register [value]", + }, + COMMAND_REGISTRATION_DONE +}; +static const struct command_registration xscale_any_command_handlers[] = { + { + .name = "debug_handler", + .handler = xscale_handle_debug_handler_command, + .mode = COMMAND_ANY, + .help = "Change address used for debug handler.", + .usage = "target address", + }, + { + .name = "cache_clean_address", + .handler = xscale_handle_cache_clean_address_command, + .mode = COMMAND_ANY, + .help = "Change address used for cleaning data cache.", + .usage = "address", + }, + { + .chain = xscale_exec_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; +static const struct command_registration xscale_command_handlers[] = { + { + .chain = arm_command_handlers, + }, + { + .name = "xscale", + .mode = COMMAND_ANY, + .help = "xscale command group", + .chain = xscale_any_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; -target_type_t xscale_target = +struct target_type xscale_target = { .name = "xscale", @@ -3623,13 +3856,17 @@ target_type_t xscale_target = .deassert_reset = xscale_deassert_reset, .soft_reset_halt = NULL, - .get_gdb_reg_list = armv4_5_get_gdb_reg_list, + /* REVISIT on some cores, allow exporting iwmmxt registers ... */ + .get_gdb_reg_list = arm_get_gdb_reg_list, .read_memory = xscale_read_memory, + .read_phys_memory = xscale_read_phys_memory, .write_memory = xscale_write_memory, + .write_phys_memory = xscale_write_phys_memory, .bulk_write_memory = xscale_bulk_write_memory, - .checksum_memory = arm7_9_checksum_memory, - .blank_check_memory = arm7_9_blank_check_memory, + + .checksum_memory = arm_checksum_memory, + .blank_check_memory = arm_blank_check_memory, .run_algorithm = armv4_5_run_algorithm, @@ -3638,7 +3875,7 @@ target_type_t xscale_target = .add_watchpoint = xscale_add_watchpoint, .remove_watchpoint = xscale_remove_watchpoint, - .register_commands = xscale_register_commands, + .commands = xscale_command_handlers, .target_create = xscale_target_create, .init_target = xscale_init_target,