X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fxscale.c;h=e0ce400b46101a5b480467693deccf0757a64db4;hp=ddc73d20cd6538ae858718b65b849c2fc5aeb648;hb=f1f8d9a6c9b1fd35d79627b568faa2409f13311f;hpb=ee139164114460d5c4c1a720e28740a7dceca712

diff --git a/src/target/xscale.c b/src/target/xscale.c
index ddc73d20cd..e0ce400b46 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -160,8 +160,7 @@ static int xscale_verify_pointer(struct command_context *cmd_ctx,
 
 static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr, tap_state_t end_state)
 {
-	if (tap == NULL)
-		return ERROR_FAIL;
+	assert (tap != NULL);
 
 	if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
 	{
@@ -245,7 +244,7 @@ static int xscale_read_dcsr(struct target *target)
 static void xscale_getbuf(jtag_callback_data_t arg)
 {
 	uint8_t *in = (uint8_t *)arg;
-	*((uint32_t *)in) = buf_get_u32(in, 0, 32);
+	*((uint32_t *)arg) = buf_get_u32(in, 0, 32);
 }
 
 static int xscale_receive(struct target *target, uint32_t *buffer, int num_words)
@@ -896,7 +895,7 @@ static int xscale_debug_entry(struct target *target)
 	struct arm *armv4_5 = &xscale->armv4_5_common;
 	uint32_t pc;
 	uint32_t buffer[10];
-	int i;
+	unsigned i;
 	int retval;
 	uint32_t moe;
 
@@ -965,6 +964,11 @@ static int xscale_debug_entry(struct target *target)
 		r->valid = true;
 	}
 
+	/* mark xscale regs invalid to ensure they are retrieved from the
+	 * debug handler if requested  */
+	for (i = 0; i < xscale->reg_cache->num_regs; i++)
+	   xscale->reg_cache->reg_list[i].valid = 0;
+
 	/* examine debug reason */
 	xscale_read_dcsr(target);
 	moe = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 2, 3);
@@ -1975,6 +1979,7 @@ static int xscale_write_memory(struct target *target, uint32_t address,
 		if ((retval = xscale_send_u32(target, 0x60)) != ERROR_OK)
 			return retval;
 
+		LOG_ERROR("data abort writing memory");
 		return ERROR_TARGET_DATA_ABORT;
 	}
 
@@ -2002,25 +2007,33 @@ static int xscale_bulk_write_memory(struct target *target, uint32_t address,
 	return xscale_write_memory(target, address, 4, count, buffer);
 }
 
-static uint32_t xscale_get_ttb(struct target *target)
+static int xscale_get_ttb(struct target *target, uint32_t *result)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
 	uint32_t ttb;
+	int retval;
 
-	xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_TTB]);
+	retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_TTB]);
+	if (retval != ERROR_OK)
+		return retval;
 	ttb = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_TTB].value, 0, 32);
 
-	return ttb;
+	*result = ttb;
+
+	return ERROR_OK;
 }
 
-static void xscale_disable_mmu_caches(struct target *target, int mmu,
+static int xscale_disable_mmu_caches(struct target *target, int mmu,
 		int d_u_cache, int i_cache)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
 	uint32_t cp15_control;
+	int retval;
 
 	/* read cp15 control register */
-	xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
+	retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
+	if (retval !=ERROR_OK)
+		return retval;
 	cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
 
 	if (mmu)
@@ -2029,11 +2042,17 @@ static void xscale_disable_mmu_caches(struct target *target, int mmu,
 	if (d_u_cache)
 	{
 		/* clean DCache */
-		xscale_send_u32(target, 0x50);
-		xscale_send_u32(target, xscale->cache_clean_address);
+		retval = xscale_send_u32(target, 0x50);
+		if (retval !=ERROR_OK)
+			return retval;
+		retval = xscale_send_u32(target, xscale->cache_clean_address);
+		if (retval !=ERROR_OK)
+			return retval;
 
 		/* invalidate DCache */
-		xscale_send_u32(target, 0x51);
+		retval = xscale_send_u32(target, 0x51);
+		if (retval !=ERROR_OK)
+			return retval;
 
 		cp15_control &= ~0x4U;
 	}
@@ -2041,25 +2060,33 @@ static void xscale_disable_mmu_caches(struct target *target, int mmu,
 	if (i_cache)
 	{
 		/* invalidate ICache */
-		xscale_send_u32(target, 0x52);
+		retval = xscale_send_u32(target, 0x52);
+		if (retval !=ERROR_OK)
+			return retval;
 		cp15_control &= ~0x1000U;
 	}
 
 	/* write new cp15 control register */
-	xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
+	retval = xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
+	if (retval !=ERROR_OK)
+		return retval;
 
 	/* execute cpwait to ensure outstanding operations complete */
-	xscale_send_u32(target, 0x53);
+	retval = xscale_send_u32(target, 0x53);
+	return retval;
 }
 
-static void xscale_enable_mmu_caches(struct target *target, int mmu,
+static int xscale_enable_mmu_caches(struct target *target, int mmu,
 		int d_u_cache, int i_cache)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
 	uint32_t cp15_control;
+	int retval;
 
 	/* read cp15 control register */
-	xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
+	retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
+	if (retval !=ERROR_OK)
+		return retval;
 	cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
 
 	if (mmu)
@@ -2072,10 +2099,13 @@ static void xscale_enable_mmu_caches(struct target *target, int mmu,
 		cp15_control |= 0x1000U;
 
 	/* write new cp15 control register */
-	xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
+	retval = xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
+	if (retval !=ERROR_OK)
+		return retval;
 
 	/* execute cpwait to ensure outstanding operations complete */
-	xscale_send_u32(target, 0x53);
+	retval = xscale_send_u32(target, 0x53);
+	return retval;
 }
 
 static int xscale_set_breakpoint(struct target *target,
@@ -2112,9 +2142,9 @@ static int xscale_set_breakpoint(struct target *target,
 			breakpoint->set = 2;	/* breakpoint set on second breakpoint register */
 		}
 		else
-		{
+		{	/* bug: availability previously verified in xscale_add_breakpoint() */
 			LOG_ERROR("BUG: no hardware comparator available");
-			return ERROR_OK;
+			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 		}
 	}
 	else if (breakpoint->type == BKPT_SOFT)
@@ -2140,7 +2170,7 @@ static int xscale_set_breakpoint(struct target *target,
 				return retval;
 			}
 			/* write the bkpt instruction in target endianness (arm7_9->arm_bkpt is host endian) */
-			if ((retval = target_write_u32(target, breakpoint->address, xscale->thumb_bkpt)) != ERROR_OK)
+			if ((retval = target_write_u16(target, breakpoint->address, xscale->thumb_bkpt)) != ERROR_OK)
 			{
 				return retval;
 			}
@@ -2163,13 +2193,13 @@ static int xscale_add_breakpoint(struct target *target,
 
 	if ((breakpoint->type == BKPT_HARD) && (xscale->ibcr_available < 1))
 	{
-		LOG_INFO("no breakpoint unit available for hardware breakpoint");
+		LOG_ERROR("no breakpoint unit available for hardware breakpoint");
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
 
 	if ((breakpoint->length != 2) && (breakpoint->length != 4))
 	{
-		LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
+		LOG_ERROR("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
 
@@ -2178,7 +2208,7 @@ static int xscale_add_breakpoint(struct target *target,
 		xscale->ibcr_available--;
 	}
 
-	return ERROR_OK;
+	return xscale_set_breakpoint(target, breakpoint);
 }
 
 static int xscale_unset_breakpoint(struct target *target,
@@ -2247,7 +2277,7 @@ static int xscale_remove_breakpoint(struct target *target, struct breakpoint *br
 
 	if (target->state != TARGET_HALTED)
 	{
-		LOG_WARNING("target not halted");
+		LOG_ERROR("target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
@@ -2266,18 +2296,16 @@ static int xscale_set_watchpoint(struct target *target,
 		struct watchpoint *watchpoint)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
-	uint8_t enable = 0;
+	uint32_t enable = 0;
 	struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
 	uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32);
 
 	if (target->state != TARGET_HALTED)
 	{
-		LOG_WARNING("target not halted");
+		LOG_ERROR("target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	xscale_get_reg(dbcon);
-
 	switch (watchpoint->rw)
 	{
 		case WPT_READ:
@@ -2293,6 +2321,24 @@ static int xscale_set_watchpoint(struct target *target,
 			LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
 	}
 
+	/* For watchpoint across more than one word, both DBR registers must
+	   be enlisted, with the second used as a mask. */
+	if (watchpoint->length > 4)
+	{
+	   if (xscale->dbr0_used || xscale->dbr1_used) 
+	   {
+		  LOG_ERROR("BUG: sufficient hardware comparators unavailable");
+		  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+	   }
+
+	   /* Write mask value to DBR1, based on the length argument.
+		* Address bits ignored by the comparator are those set in mask. */
+	   xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR1],
+						  watchpoint->length - 1);
+	   xscale->dbr1_used = 1;
+	   enable |= 0x100;			/* DBCON[M] */
+	}
+
 	if (!xscale->dbr0_used)
 	{
 		xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR0], watchpoint->address);
@@ -2312,7 +2358,7 @@ static int xscale_set_watchpoint(struct target *target,
 	else
 	{
 		LOG_ERROR("BUG: no hardware comparator available");
-		return ERROR_OK;
+		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
 
 	return ERROR_OK;
@@ -2325,16 +2371,44 @@ static int xscale_add_watchpoint(struct target *target,
 
 	if (xscale->dbr_available < 1)
 	{
-		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+	   LOG_ERROR("no more watchpoint registers available");
+	   return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
 
-	if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
+	if (watchpoint->value)
+	   LOG_WARNING("xscale does not support value, mask arguments; ignoring");
+
+	/* check that length is a power of two */
+	for (uint32_t len = watchpoint->length; len != 1; len /= 2)
 	{
-		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+	   if (len % 2)
+	   {
+		  LOG_ERROR("xscale requires that watchpoint length is a power of two");
+		  return ERROR_COMMAND_ARGUMENT_INVALID;
+	   }
 	}
 
-	xscale->dbr_available--;
+	if (watchpoint->length == 4) /* single word watchpoint */
+	{
+	   xscale->dbr_available--; /* one DBR reg used */
+	   return ERROR_OK;
+	}
 
+	/* watchpoints across multiple words require both DBR registers */
+	if (xscale->dbr_available < 2)
+	{
+	   LOG_ERROR("insufficient watchpoint registers available");
+	   return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+	}
+	
+	if (watchpoint->length > watchpoint->address)
+	{
+	   LOG_ERROR("xscale does not support watchpoints with length "
+				 "greater than address");
+	   return ERROR_COMMAND_ARGUMENT_INVALID;
+	}
+	   
+	xscale->dbr_available = 0;
 	return ERROR_OK;
 }
 
@@ -2359,7 +2433,14 @@ static int xscale_unset_watchpoint(struct target *target,
 
 	if (watchpoint->set == 1)
 	{
-		dbcon_value &= ~0x3;
+	   if (watchpoint->length > 4)
+	   {
+		  dbcon_value &= ~0x103; /* clear DBCON[M] as well */
+		  xscale->dbr1_used = 0; /* DBR1 was used for mask */
+	   }
+	   else
+		  dbcon_value &= ~0x3;
+
 		xscale_set_reg_u32(dbcon, dbcon_value);
 		xscale->dbr0_used = 0;
 	}
@@ -2380,7 +2461,7 @@ static int xscale_remove_watchpoint(struct target *target, struct watchpoint *wa
 
 	if (target->state != TARGET_HALTED)
 	{
-		LOG_WARNING("target not halted");
+		LOG_ERROR("target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
@@ -2389,6 +2470,9 @@ static int xscale_remove_watchpoint(struct target *target, struct watchpoint *wa
 		xscale_unset_watchpoint(target, watchpoint);
 	}
 
+	if (watchpoint->length > 4)
+	   xscale->dbr_available++;	/* both DBR regs now available */
+	
 	xscale->dbr_available++;
 
 	return ERROR_OK;
@@ -3173,21 +3257,18 @@ static int xscale_virt2phys(struct target *target,
 		uint32_t virtual, uint32_t *physical)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
-	int type;
 	uint32_t cb;
-	int domain;
-	uint32_t ap;
 
 	if (xscale->common_magic != XSCALE_COMMON_MAGIC) {
 		LOG_ERROR(xscale_not);
 		return ERROR_TARGET_INVALID;
 	}
 
-	uint32_t ret = armv4_5_mmu_translate_va(target, &xscale->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
-	if (type == -1)
-	{
-		return ret;
-	}
+	uint32_t ret;
+	int retval = armv4_5_mmu_translate_va(target, &xscale->armv4_5_mmu,
+			virtual, &cb, &ret);
+	if (retval != ERROR_OK)
+		return retval;
 	*physical = ret;
 	return ERROR_OK;
 }