X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Fboard%2Fmini2440.cfg;h=8497bddf424674b92cadabbc460598146da57b94;hp=0b1d8812d273ed91730080d56019fa195bea1979;hb=71af49ca7fb11b0bd0c1ba9578826f49288b68ef;hpb=86a7d813a165fda2816b8152342219b6c4ae2fc4 diff --git a/tcl/board/mini2440.cfg b/tcl/board/mini2440.cfg index 0b1d8812d2..8497bddf42 100644 --- a/tcl/board/mini2440.cfg +++ b/tcl/board/mini2440.cfg @@ -1,7 +1,7 @@ #------------------------------------------------------------------------- # Mini2440 Samsung s3c2440A Processor with 64MB DRAM, 64MB NAND, 2 MB N0R # NOTE: Configured for NAND boot (switch S2 in NANDBOOT) -# 64 MB NAND (Samsung K9D1208V0M) +# 64 MB NAND (Samsung K9D1208V0M) # B Findlay 08/09 # # ----------- Important notes to help you on your way ---------- @@ -9,9 +9,9 @@ # NOR/NAND Boot Switch - I have not read the vivi source, but from # what I could tell from reading the registers it appears that vivi # loads itself into DRAM and then flips NFCONT (0x4E000004) bits -# Mode (bit 0 = 1), and REG_nCE (bit 1 = 0) which maps the NAND -# FLASH at the bottom 64MB of memory. This essentially takes the -# NOR Flash out of the circuit so you can't trash it. +# Mode (bit 0 = 1), and REG_nCE (bit 1 = 0) which maps the NAND +# FLASH at the bottom 64MB of memory. This essentially takes the +# NOR Flash out of the circuit so you can't trash it. # # I adapted the samsung_s3c2440.cfg file which is why I did not # include "source [find target/samsung_s3c2440.cfg]". I believe @@ -22,9 +22,9 @@ # JTAG ADAPTER SPECIFIC # IMPORTANT! Any JTAG device that uses ADAPTIVE CLOCKING will likely # FAIL as the pin RTCK on the mini2440 10 pin JTAG Conn doesn't exist. -# This is Pin 11 (RTCK) on 20 pin JTAG connector. Therefore it is +# This is Pin 11 (RTCK) on 20 pin JTAG connector. Therefore it is # necessary to FORCE setting the clock. Normally this should be configured -# in the openocd.cfg file, but was placed here as it can be a tough +# in the openocd.cfg file, but was placed here as it can be a tough # problem to figure out. THIS MAY NOT FIX YOUR PROBLEM.. I modified # the openOCD driver jlink.c and posted it here. It may eventually end # up changed in openOCD, but its a hack in the driver and really should @@ -42,21 +42,21 @@ # But it should get you way ahead of the game from where I started. # If you find problems (and fixes) please post them to # openocd-development@lists.berlios.de and join the developers and -# check in fixes to this and anything else you find. I do not -# provide support, but if you ask really nice and I see anything +# check in fixes to this and anything else you find. I do not +# provide support, but if you ask really nice and I see anything # obvious I will tell you.. mostly just dig, fix, and submit to openocd. -# +# # best! brfindla@yahoo.com Nashua, NH USA # # Recommended resources: # - first two are the best Mini2440 resources anywhere # - maintained by buserror... thanks guy! # -# http://bliterness.blogspot.com/ +# http://bliterness.blogspot.com/ # http://code.google.com/p/mini2440/ # # others.... -# +# # http://forum.sparkfun.com/viewforum.php?f=18 # http://labs.kernelconcepts.de/Publications/Micro24401/ # http://www.friendlyarm.net/home @@ -75,19 +75,19 @@ # Target configuration for the Samsung 2440 system on chip # Tested on a S3C2440 Evaluation board by keesj # Processor : ARM920Tid(wb) rev 0 (v4l) -# Info: JTAG tap: s3c2440.cpu tap/device found: 0x0032409d +# Info: JTAG tap: s3c2440.cpu tap/device found: 0x0032409d # (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0) #------------------------------------------------------------------------- -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME s3c2440 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { # this defaults to a bigendian set _ENDIAN little } @@ -108,16 +108,16 @@ $_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area- #reset configuration jtag_nsrst_delay 100 -jtag_ntrst_delay 100 +jtag_ntrst_delay 100 reset_config trst_and_srst #------------------------------------------------------------------------- # JTAG ADAPTER SPECIFIC -# IMPORTANT! See README at top of this file. +# IMPORTANT! See README at top of this file. #------------------------------------------------------------------------- - jtag_khz 12000 - jtag interface + jtag_khz 12000 + jtag interface #------------------------------------------------------------------------- # GDB Setup @@ -125,23 +125,23 @@ reset_config trst_and_srst gdb_port 3333 gdb_detach resume - gdb_breakpoint_override hard + gdb_breakpoint_override hard gdb_memory_map enable - gdb_flash_program enable + gdb_flash_program enable #------------------------------------------------ # ARM SPECIFIC #------------------------------------------------ - targets + targets # arm7_9 dcc_downloads enable # arm7_9 fast_memory_access enable - - - nand device s3c2440 0 + + + nand device s3c2440 0 jtag_nsrst_delay 100 - jtag_ntrst_delay 100 + jtag_ntrst_delay 100 reset_config trst_and_srst init @@ -180,59 +180,59 @@ proc init_2440 { } { # OM2 OM3 pulled to ground so main clock and # usb clock are off 12mHz xtal #----------------------------------------------- - + arm920t mww_phys 0x4C000014 0x00000005 # Clock Divider control Reg arm920t mww_phys 0x4C000000 0xFFFFFFFF # LOCKTIME count register arm920t mww_phys 0x4C000008 0x00038022 # UPPLCON USB clock config Reg arm920t mww_phys 0x4C000004 0x0007F021 # MPPLCON Proc clock config Reg - + #----------------------------------------------- # Configure Memory controller # BWSCON configures all banks, NAND, NOR, DRAM # DRAM - 64MB - 32 bit bus, uses BANKCON6 BANKCON7 #----------------------------------------------- - + arm920t mww_phys 0x48000000 0x22111112 # BWSCON - Bank and Bus Width arm920t mww_phys 0x48000010 0x00001112 # BANKCON4 - ? - arm920t mww_phys 0x4800001c 0x00018009 # BANKCON6 - DRAM - arm920t mww_phys 0x48000020 0x00018009 # BANKCON7 - DRAM - arm920t mww_phys 0x48000024 0x008E04EB # REFRESH - DRAM - arm920t mww_phys 0x48000028 0x000000B2 # BANKSIZE - DRAM - arm920t mww_phys 0x4800002C 0x00000030 # MRSRB6 - DRAM - arm920t mww_phys 0x48000030 0x00000030 # MRSRB7 - DRAM - + arm920t mww_phys 0x4800001c 0x00018009 # BANKCON6 - DRAM + arm920t mww_phys 0x48000020 0x00018009 # BANKCON7 - DRAM + arm920t mww_phys 0x48000024 0x008E04EB # REFRESH - DRAM + arm920t mww_phys 0x48000028 0x000000B2 # BANKSIZE - DRAM + arm920t mww_phys 0x4800002C 0x00000030 # MRSRB6 - DRAM + arm920t mww_phys 0x48000030 0x00000030 # MRSRB7 - DRAM + #----------------------------------------------- # Now port configuration for enables for memory # and other stuff. #----------------------------------------------- - + arm920t mww_phys 0x56000000 0x007FFFFF # GPACON - - arm920t mww_phys 0x56000010 0x00295559 # GPBCON + + arm920t mww_phys 0x56000010 0x00295559 # GPBCON arm920t mww_phys 0x56000018 0x000003FF # GPBUP (PULLUP ENABLE) - arm920t mww_phys 0x56000014 0x000007C2 # GPBDAT - - arm920t mww_phys 0x56000020 0xAAAAA6AA # GPCCON + arm920t mww_phys 0x56000014 0x000007C2 # GPBDAT + + arm920t mww_phys 0x56000020 0xAAAAA6AA # GPCCON arm920t mww_phys 0x56000028 0x0000FFFF # GPCUP - arm920t mww_phys 0x56000024 0x00000020 # GPCDAT - - arm920t mww_phys 0x56000030 0xAAAAAAAA # GPDCON - arm920t mww_phys 0x56000038 0x0000FFFF # GPDUP - - arm920t mww_phys 0x56000040 0xAAAAAAAA # GPECON - arm920t mww_phys 0x56000048 0x0000FFFF # GPEUP - - arm920t mww_phys 0x56000050 0x00001555 # GPFCON - arm920t mww_phys 0x56000058 0x0000007F # GPFUP - arm920t mww_phys 0x56000054 0x00000000 # GPFDAT - - arm920t mww_phys 0x56000060 0x00150114 # GPGCON - arm920t mww_phys 0x56000068 0x0000007F # GPGUP - - arm920t mww_phys 0x56000070 0x0015AAAA # GPHCON - arm920t mww_phys 0x56000078 0x000003FF # GPGUP - -} + arm920t mww_phys 0x56000024 0x00000020 # GPCDAT + + arm920t mww_phys 0x56000030 0xAAAAAAAA # GPDCON + arm920t mww_phys 0x56000038 0x0000FFFF # GPDUP + + arm920t mww_phys 0x56000040 0xAAAAAAAA # GPECON + arm920t mww_phys 0x56000048 0x0000FFFF # GPEUP + + arm920t mww_phys 0x56000050 0x00001555 # GPFCON + arm920t mww_phys 0x56000058 0x0000007F # GPFUP + arm920t mww_phys 0x56000054 0x00000000 # GPFDAT + + arm920t mww_phys 0x56000060 0x00150114 # GPGCON + arm920t mww_phys 0x56000068 0x0000007F # GPGUP + + arm920t mww_phys 0x56000070 0x0015AAAA # GPHCON + arm920t mww_phys 0x56000078 0x000003FF # GPGUP + +} @@ -243,7 +243,7 @@ proc flash_config { } { #----------------------------------------- halt - + #flash configuration (K9D1208V0M: 512Mbit, x8, 3.3V, Mode: Normal, 1st gen) nand probe 0 nand list @@ -275,8 +275,8 @@ proc load_uboot { } { echo "---- http://repo.or.cz/w/u-boot-openmoko/mini2440.git ---" echo "---- Also this: ---" echo "---- http://code.google.com/p/mini2440/wiki/MiniBringup --" - echo "----------------------------------------------------------" - + echo "----------------------------------------------------------" + init_2440 echo "Loading /tftpboot/u-boot-nand512.bin" load_image /tftpboot/u-boot-nand512.bin 0x33f80000 bin