X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Fboard%2Folimex_sam9_l9260.cfg;h=72dce87b1c2d8ecdb57d66a6bfa704b1070940d1;hp=7c4b2ccb0a63bf4424b1648edafe588a83a8e4bf;hb=HEAD;hpb=900d745567809d9f0163cfde5832b10ec0581a0e diff --git a/tcl/board/olimex_sam9_l9260.cfg b/tcl/board/olimex_sam9_l9260.cfg index 7c4b2ccb0a..7491a0ed52 100644 --- a/tcl/board/olimex_sam9_l9260.cfg +++ b/tcl/board/olimex_sam9_l9260.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + ################################################################################ # Olimex SAM9-L9260 Development Board # @@ -23,50 +25,50 @@ $_TARGETNAME configure -event reset-start { # RCLK is not supported. jtag_rclk 5 halt - - # RSTC_MR : enable user reset, reset length is 64 slow clock cycles. MMU may + + # RSTC_MR : enable user reset, reset length is 64 slow clock cycles. MMU may # be enabled... use physical address. mww phys 0xfffffd08 0xa5000501 } $_TARGETNAME configure -event reset-init { - mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog - + mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog + ## # Clock configuration for 99.328 MHz main clock. ## - puts "Setting up clock" - mww 0xfffffc20 0x00004001 # CKGR_MOR : enable main oscillator, 512 slow clock startup - sleep 20 # wait 20 ms (need 15.6 ms for startup) - mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator (18.432 MHz) - sleep 10 # wait 10 ms - mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR : 18.432 MHz / 9 * 97 = 198.656 MHz, 63 slow clock startup - sleep 20 # wait 20 ms (need 1.9 ms for startup) - mww 0xfffffc30 0x00000101 # PMC_MCKR : no scale on proc clock, master is proc / 2 - sleep 10 # wait 10 ms - mww 0xfffffc30 0x00000102 # PMC_MCKR : switch to PLLA (99.328 MHz) - + echo "Setting up clock" + mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable main oscillator, 512 slow clock startup + sleep 20 ;# wait 20 ms (need 15.6 ms for startup) + mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator (18.432 MHz) + sleep 10 ;# wait 10 ms + mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR : 18.432 MHz / 9 * 97 = 198.656 MHz, 63 slow clock startup + sleep 20 ;# wait 20 ms (need 1.9 ms for startup) + mww 0xfffffc30 0x00000101 ;# PMC_MCKR : no scale on proc clock, master is proc / 2 + sleep 10 ;# wait 10 ms + mww 0xfffffc30 0x00000102 ;# PMC_MCKR : switch to PLLA (99.328 MHz) + # Increase JTAG speed to 6 MHz if RCLK is not supported. jtag_rclk 6000 - - arm7_9 dcc_downloads enable # Enable faster DCC downloads. - + + arm7_9 dcc_downloads enable ;# Enable faster DCC downloads. + ## # SDRAM configuration for 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks. ## - puts "Configuring SDRAM" - mww 0xfffff870 0xffff0000 # PIOC_ASR : select peripheral function for D15..D31 - mww 0xfffff804 0xffff0000 # PIOC_PDR : disable PIO function for D15..D31 - - mww 0xffffef1c 0x00010002 # EBI_CSA : assign EBI CS1 to SDRAM, VDDIOMSEL set for +3V3 memory - - mww 0xffffea08 0x85237259 # SDRAMC_CR : configure SDRAM for Samsung chips - - mww 0xffffea00 0x1 # SDRAMC_MR : issue NOP command + echo "Configuring SDRAM" + mww 0xfffff870 0xffff0000 ;# PIOC_ASR : select peripheral function for D15..D31 + mww 0xfffff804 0xffff0000 ;# PIOC_PDR : disable PIO function for D15..D31 + + mww 0xffffef1c 0x00010002 ;# EBI_CSA : assign EBI CS1 to SDRAM, VDDIOMSEL set for +3V3 memory + + mww 0xffffea08 0x85237259 ;# SDRAMC_CR : configure SDRAM for Samsung chips + + mww 0xffffea00 0x1 ;# SDRAMC_MR : issue NOP command mww 0x20000000 0 - mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command + mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command mww 0x20000000 0 - mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' command + mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' command mww 0x20000000 0 mww 0xffffea00 0x4 mww 0x20000000 0 @@ -82,54 +84,54 @@ $_TARGETNAME configure -event reset-init { mww 0x20000000 0 mww 0xffffea00 0x4 mww 0x20000000 0 - mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command + mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command mww 0x20000000 0 - mww 0xffffea00 0x0 # SDRAMC_MR : normal mode + mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode mww 0x20000000 0 - - mww 0xffffea04 0x2b6 # SDRAMC_TR : set refresh timer count to 7 us + + mww 0xffffea04 0x2b6 ;# SDRAMC_TR : set refresh timer count to 7 us ## # NAND Flash Configuration for 1 x Samsung K9F4G08U0M, 512M x 8Bit. ## - puts "Configuring NAND flash" + echo "Configuring NAND flash" mww 0xfffffc10 0x00000010 ;# PMC_PCER : enable PIOC clock mww 0xfffff800 0x00006000 ;# PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS) mww 0xfffff810 0x00004000 ;# PIOC_OER : enable output on 14 mww 0xfffff814 0x00002000 ;# PIOC_ODR : disable output on 13 mww 0xfffff830 0x00004000 ;# PIOC_SODR : set 14 to disable NAND mww 0xfffff864 0x00002000 ;# PIOC_PUER : enable pull-up on 13 - + mww 0xffffef1c 0x0001000A ;# EBI_CSA : assign EBI CS3 to NAND, same settings as before - + mww 0xffffec30 0x00010001 ;# SMC_SETUP3 : 1 clock cycle setup for NRD and NWE mww 0xffffec34 0x03030303 ;# SMC_PULSE3 : 3 clock cycle pulse for all signals mww 0xffffec38 0x00050005 ;# SMC_CYCLE3 : 5 clock cycle NRD and NWE cycle - mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW, + mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW, # 3 TDF cycles, no optimization - + mww 0xffffe800 0x00000001 ;# ECC_CR : reset the ECC parity registers mww 0xffffe804 0x00000002 ;# ECC_MR : page size is 2112 words (word is 8 bits) - + nand probe at91sam9260.flash - + ## # Dataflash configuration for 1 x Atmel AT45DB161D, 16Mbit ## - puts "Setting up dataflash" - mww 0xfffff404 0x00000807 ;# PIOA_PDR : disable PIO function for 0(SPI0_MISO), 1(SPI0_MOSI), + echo "Setting up dataflash" + mww 0xfffff404 0x00000807 ;# PIOA_PDR : disable PIO function for 0(SPI0_MISO), 1(SPI0_MOSI), # 2(SPI0_SPCK), and 11(SPI0_NPCS1) mww 0xfffff470 0x00000007 ;# PIOA_ASR : select peripheral A function for 0, 1, and 2 mww 0xfffff474 0x00000800 ;# PIOA_BSR : select peripheral B function for 11 mww 0xfffffc10 0x00001000 ;# PMC_PCER : enable SPI0 clock - + mww 0xfffc8000 0x00000080 ;# SPI0_CR : software reset SPI0 mww 0xfffc8000 0x00000080 ;# SPI0_CR : again to be sure mww 0xfffc8004 0x000F0011 ;# SPI0_MR : master mode with nothing selected - - mww 0xfffc8034 0x011a0302 ;# SPI0_CSR1 : capture on leading edge, 8-bits/tx. 33MHz baud, + + mww 0xfffc8034 0x011a0302 ;# SPI0_CSR1 : capture on leading edge, 8-bits/tx. 33MHz baud, # 250ns delay before SPCK, 250ns b/n tx - + mww 0xfffc8004 0x000D0011 ;# SPI0_MR : same config, select NPCS1 mww 0xfffc8000 0x00000001 ;# SPI0_CR : enable SPI0 }