X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Fboard%2Fpxa255_sst.cfg;h=49cad5db74d281469803928175b3744f8c5ef3f4;hp=44f34ca1bb86223d651bc1e2b39ddc63d4fbbfda;hb=1c2e3d41de30c5e47d3fc8eda3de0a0a8229895a;hpb=b559b273b526b3077b3ca219eecc8df9f86efac0

diff --git a/tcl/board/pxa255_sst.cfg b/tcl/board/pxa255_sst.cfg
index 44f34ca1bb..49cad5db74 100644
--- a/tcl/board/pxa255_sst.cfg
+++ b/tcl/board/pxa255_sst.cfg
@@ -17,75 +17,75 @@ set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME cfi 0x00000000 0x80000 2 2 $_TARGETNAME jedec_probe
 
 proc pxa255_sst_init {} {
-	xscale cp15   15      0x00002001  #Enable CP0 and CP13 access
+	xscale cp15   15      0x00002001  ;#Enable CP0 and CP13 access
 	#
 	# setup GPIO
 	#
-	mww    0x40E00018  0x00008000  #CPSR0
+	mww    0x40E00018  0x00008000  ;#CPSR0
 	sleep   20
-	mww    0x40E0001C  0x00000002  #GPSR1
+	mww    0x40E0001C  0x00000002  ;#GPSR1
 	sleep   20
-	mww    0x40E00020  0x00000008  #GPSR2
+	mww    0x40E00020  0x00000008  ;#GPSR2
 	sleep   20
-	mww    0x40E0000C  0x00008000  #GPDR0
+	mww    0x40E0000C  0x00008000  ;#GPDR0
 	sleep   20
-	mww    0x40E00054  0x80000000  #GAFR0_L
+	mww    0x40E00054  0x80000000  ;#GAFR0_L
 	sleep   20
-	mww    0x40E00058  0x00188010  #GAFR0_H
+	mww    0x40E00058  0x00188010  ;#GAFR0_H
 	sleep   20
-	mww    0x40E0005C  0x60908018  #GAFR1_L
+	mww    0x40E0005C  0x60908018  ;#GAFR1_L
 	sleep   20
-	mww    0x40E0000C  0x0280E000  #GPDR0
+	mww    0x40E0000C  0x0280E000  ;#GPDR0
 	sleep   20
-	mww    0x40E00010  0x821C88B2  #GPDR1
+	mww    0x40E00010  0x821C88B2  ;#GPDR1
 	sleep   20
-	mww    0x40E00014  0x000F03DB  #GPDR2
+	mww    0x40E00014  0x000F03DB  ;#GPDR2
 	sleep   20
-	mww    0x40E00000  0x000F03DB  #GPLR0
+	mww    0x40E00000  0x000F03DB  ;#GPLR0
 	sleep   20
 
 
-	mww    0x40F00004  0x00000020  #PSSR
+	mww    0x40F00004  0x00000020  ;#PSSR
 	sleep   20
 
 	#
 	# setup memory controller
 	#
-	mww    0x48000008  0x01111998  #MSC0
+	mww    0x48000008  0x01111998  ;#MSC0
 	sleep   20
-	mww    0x48000010  0x00047ff0  #MSC2
+	mww    0x48000010  0x00047ff0  ;#MSC2
 	sleep   20
-	mww    0x48000014  0x00000000  #MECR
+	mww    0x48000014  0x00000000  ;#MECR
 	sleep   20
-	mww    0x48000028  0x00010504  #MCMEM0
+	mww    0x48000028  0x00010504  ;#MCMEM0
 	sleep   20
-	mww    0x4800002C  0x00010504  #MCMEM1
+	mww    0x4800002C  0x00010504  ;#MCMEM1
 	sleep   20
-	mww    0x48000030  0x00010504  #MCATT0
+	mww    0x48000030  0x00010504  ;#MCATT0
 	sleep   20
-	mww    0x48000034  0x00010504  #MCATT1
+	mww    0x48000034  0x00010504  ;#MCATT1
 	sleep   20
-	mww    0x48000038  0x00004715  #MCIO0
+	mww    0x48000038  0x00004715  ;#MCIO0
 	sleep   20
-	mww    0x4800003C  0x00004715  #MCIO1
+	mww    0x4800003C  0x00004715  ;#MCIO1
 	sleep   20
 	#
-	mww    0x48000004  0x03CA4018  #MDREF
+	mww    0x48000004  0x03CA4018  ;#MDREF
 	sleep   20
-	mww    0x48000004  0x004B4018  #MDREF
+	mww    0x48000004  0x004B4018  ;#MDREF
 	sleep   20
-	mww    0x48000004  0x000B4018  #MDREF
+	mww    0x48000004  0x000B4018  ;#MDREF
 	sleep   20
-	mww    0x48000004  0x000BC018  #MDREF
+	mww    0x48000004  0x000BC018  ;#MDREF
 	sleep   20
-	mww    0x48000000  0x00001AC8  #MDCNFG
+	mww    0x48000000  0x00001AC8  ;#MDCNFG
 	sleep   20
 
 	sleep   20
 
-	mww    0x48000000  0x00001AC9  #MDCNFG
+	mww    0x48000000  0x00001AC9  ;#MDCNFG
 	sleep   20
-	mww    0x48000040  0x00000000  #MDMRS
+	mww    0x48000040  0x00000000  ;#MDMRS
 	sleep   20
 }
 
@@ -96,4 +96,4 @@ reset_config trst_and_srst
 adapter_nsrst_delay 200
 jtag_ntrst_delay 200
 
-#xscale debug_handler 0  0xFFFF0800      # debug handler base address
+#xscale debug_handler 0  0xFFFF0800      ;# debug handler base address