X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Fboard%2Frsc-w910.cfg;h=636a05399d0e7ccaba93993620bfb5ca51aa07dc;hp=eba44f62d4f5aba0a0fa5e844372378158f06fe9;hb=ff555afc02d50ca57fc6e71787d34a8e985cf115;hpb=8f5e84bf8dabfddc6b853c522fdc29be90c93746

diff --git a/tcl/board/rsc-w910.cfg b/tcl/board/rsc-w910.cfg
index eba44f62d4..636a05399d 100644
--- a/tcl/board/rsc-w910.cfg
+++ b/tcl/board/rsc-w910.cfg
@@ -21,6 +21,9 @@ $_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x04000000 -wo
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME cfi 0x20000000 0x00200000 2 2 $_TARGETNAME
 
+set _NANDNAME $_CHIPNAME.nand
+nand device $_NANDNAME nuc910 $_TARGETNAME
+
 #
 # Target events
 #
@@ -31,12 +34,12 @@ $_TARGETNAME configure -event reset-init {
 	# switch on PLL for 200MHz operation
 	# running from 15MHz input clock
 	
-	mww 0xB0000200 0x00000030 # CLKEN
-	mww 0xB0000204 0x00000f3c # CLKSEL
-	mww 0xB0000208 0x05007000 # CLKDIV
-	mww 0xB000020C 0x00004f24 # PLLCON0
-	mww 0xB0000210 0x00002b63 # PLLCON1
-	mww 0xB000000C 0x08817fa6 # MFSEL
+	mww 0xB0000200 0x00000030 ;# CLKEN
+	mww 0xB0000204 0x00000f3c ;# CLKSEL
+	mww 0xB0000208 0x05007000 ;# CLKDIV
+	mww 0xB000020C 0x00004f24 ;# PLLCON0
+	mww 0xB0000210 0x00002b63 ;# PLLCON1
+	mww 0xB000000C 0x08817fa6 ;# MFSEL
 	sleep 10
 	
 	# we are now running @ 200MHz
@@ -49,15 +52,15 @@ $_TARGETNAME configure -event reset-init {
 	# map nor flash to 0x20000000
 	# map sdram to 0x00000000
 	
-	mww 0xb0001000 0x000530c1 # EBICON
-	mww 0xb0001004 0x40030084 # ROMCON
-	mww 0xb0001008 0x000010ee # SDCONF0
-	mww 0xb000100C 0x00000000 # SDCONF1
-	mww 0xb0001010 0x0000015b # SDTIME0
-	mww 0xb0001014 0x0000015b # SDTIME1
-	mww 0xb0001018 0x00000000 # EXT0CON
-	mww 0xb000101C 0x00000000 # EXT1CON
-	mww 0xb0001020 0x00000000 # EXT2CON
-	mww 0xb0001024 0x00000000 # EXT3CON
-	mww 0xb000102c 0x00ff0048 # CKSKEW
+	mww 0xb0001000 0x000530c1 ;# EBICON
+	mww 0xb0001004 0x40030084 ;# ROMCON
+	mww 0xb0001008 0x000010ee ;# SDCONF0
+	mww 0xb000100C 0x00000000 ;# SDCONF1
+	mww 0xb0001010 0x0000015b ;# SDTIME0
+	mww 0xb0001014 0x0000015b ;# SDTIME1
+	mww 0xb0001018 0x00000000 ;# EXT0CON
+	mww 0xb000101C 0x00000000 ;# EXT1CON
+	mww 0xb0001020 0x00000000 ;# EXT2CON
+	mww 0xb0001024 0x00000000 ;# EXT3CON
+	mww 0xb000102c 0x00ff0048 ;# CKSKEW
 }