X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Famdm37x.cfg;h=07e6d102bbd5654e98c92734f23ba67322764787;hp=75593af2ef4297ef47b499ee19096813e45dfadf;hb=c32f81f7186ac825652df4226646b3505b01f940;hpb=289cecebf068e7f988dcbbc8786f6acc96803963 diff --git a/tcl/target/amdm37x.cfg b/tcl/target/amdm37x.cfg index 75593af2ef..07e6d102bb 100644 --- a/tcl/target/amdm37x.cfg +++ b/tcl/target/amdm37x.cfg @@ -1,11 +1,11 @@ # -# Copyright (C) 2010 by Karl Kurbjun -# Copyright (C) 2009-2011 by Øyvind Harboe +# Copyright (C) 2010-2011 by Karl Kurbjun +# Copyright (C) 2009-2011 by Øyvind Harboe # Copyright (C) 2009 by David Brownell # Copyright (C) 2009 by Magnus Lundin # -# TI AM/DM37x -# http://www.ti.com/litv/pdf/sprugn4b +# TI AM/DM37x Technical Reference Manual (Version R) +# http://www.ti.com/lit/ug/sprugn4r/sprugn4r.pdf # # This script is based on the AM3517 initialization. It should be considered # preliminary since it needs more complete testing and only the basic @@ -21,19 +21,19 @@ if { [info exists CHIPTYPE] } { if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME $CHIPTYPE + set _CHIPNAME $CHIPTYPE } switch $CHIPTYPE { dm37x { - # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan - set _JRC_TAPID "-expected-id 0x1b89102f -expected-id 0x0b89102f" + # Primary TAP: ICEPick-C (JTAG route controller) and boundary scan + set _JRC_TAPID "-expected-id 0x2b89102f -expected-id 0x1b89102f -expected-id 0x0b89102f" } am35x { - # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan - set _JRC_TAPID "-expected-id 0x0b7ae02f" + # Primary TAP: ICEPick-C (JTAG route controller) and boundary scan + set _JRC_TAPID "-expected-id 0x0b7ae02f -expected-id 0x0b86802f" } default { error "ERROR: CHIPTYPE was set, but it was not set to a valid value. Acceptable values are \"dm37x\" or \"am35x\"." @@ -50,20 +50,20 @@ adapter_khz 10 ############################################################################### # JTAG setup # The OpenOCD commands are described in the TAP Declaration section -# http://openocd.berlios.de/doc/html/TAP-Declaration.html +# http://openocd.sourceforge.net/doc/html/TAP-Declaration.html ############################################################################### -# The AM/DM37x has an ICEpick module in it like many of TI's other devices. More -# can be read about this module in sprugn4b under chapter 27: "Debug and +# The AM/DM37x has an ICEPick module in it like many of TI's other devices. More +# can be read about this module in sprugn4r in chapter 27: "Debug and # Emulation". The module is used to route the JTAG chain to the various # subsystems in the chip. source [find target/icepick.cfg] # The TAP order should be described from the TDO connection in OpenOCD to the # TDI pin. The OpenOCD FAQ describes this in more detail: -# http://openocd.berlios.de/doc/html/FAQ.html +# http://openocd.sourceforge.net/doc/html/FAQ.html -# From SPRUGN4B CH27 the available secondary TAPs are in this order from TDO: +# From SPRUGN4R CH27 the available secondary TAPs are in this order from TDO: # # Device | TAP number # ---------|------------ @@ -77,9 +77,9 @@ source [find target/icepick.cfg] ###### # Start of Chain Description -# The Secondary TAPs all have enable functions defined for use with the ICEpick +# The Secondary TAPs all have enable functions defined for use with the ICEPick # Only the DAP is enabled. The AM37xx does not have the Sequencer or DSP but -# the TAP numbers for ICEpick do not change. +# the TAP numbers for ICEPick do not change. # # TODO: A disable function should also be added. ###### @@ -93,28 +93,28 @@ jtag configure $_CHIPNAME.dap -event tap-enable \ # These taps are only present in the DM37x series. if { $CHIPTYPE == "dm37x" } { # Secondary TAP: Sequencer (ARM968) it is not in the chain by default - # The ICEpick can be used to enable it in the chain. + # The ICEPick can be used to enable it in the chain. jtag newtap $_CHIPNAME arm2 -irlen 4 -ircapture 0x1 -irmask 0x0f -disable jtag configure $_CHIPNAME.arm2 -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 2" # Secondary TAP: C64x+ DSP - it is not in the chain by default (-disable) - # The ICEpick can be used to enable it in the chain. + # The ICEPick can be used to enable it in the chain. jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable jtag configure $_CHIPNAME.dsp -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 1" } # Secondary TAP: D2D it is not in the chain by default (-disable) -# The ICEpick can be used to enable it in the chain. +# The ICEPick can be used to enable it in the chain. # This IRLEN is probably incorrect - not sure where the documentation is. jtag newtap $_CHIPNAME d2d -irlen 4 -ircapture 0x1 -irmask 0x0f -disable jtag configure $_CHIPNAME.d2d -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 0" -# Primary TAP: ICEpick - it is closest to TDI so last in the chain +# Primary TAP: ICEPick - it is closest to TDI so last in the chain eval "jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f $_JRC_TAPID" - + ###### # End of Chain Description ###### @@ -136,12 +136,12 @@ jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap" ############################################################################### # Target Setup: # This section is described in the OpenOCD documentation under CPU Configuration -# http://openocd.berlios.de/doc/html/CPU-Configuration.html +# http://openocd.sourceforge.net/doc/html/CPU-Configuration.html ############################################################################### # Create the CPU target to be used with GDB: Cortex-A8, using DAP set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap +target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap # The DM37x has 64K of SRAM starting at address 0x4020_0000. Allow the first # 16K to be used as a scratchpad for OpenOCD. @@ -153,30 +153,39 @@ $_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000 ###### # Set the JTAG clock down to 10 kHz to be sure that it will work with the -# slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up +# slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up # *after* PLL and clock tree setup. $_TARGETNAME configure -event "reset-start" { adapter_khz 10 } -# Reset needs to be performed in in software. -# The AM/DM37x TRM (sprugn4b) describes the software reset in detail. -# PRM_RSTCTRL is described in table 3-425 on page 618. We assert RST_GS -# (bit 1 (in 31:0) ) to do a warm reset. - -# Create a vaiable for the register address -set PRM_RSTCTRL 0x48307250 +# Describe the reset assert process for openocd - this is asserted with the +# ICEPick +$_TARGETNAME configure -event "reset-assert" { -# Describe the reset assert process: A value of 2 must be written -# (assert bit 1) to the physical address of PRM_RSTCTRL. + global _CHIPNAME -$_TARGETNAME configure -event \ - reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 2" + # assert warm system reset through ICEPick + icepick_c_wreset $_CHIPNAME.jrc +} # After the reset is asserted we need to re-initialize debugging and speed up # the JTAG clock. -$_TARGETNAME configure -event \ - reset-assert-post "amdm37x_dbginit $_TARGETNAME; adapter_khz 1000" +$_TARGETNAME configure -event reset-assert-post { + + global _TARGETNAME + amdm37x_dbginit $_TARGETNAME + adapter_khz 1000 +} + +$_TARGETNAME configure -event gdb-attach { + + global _TARGETNAME + amdm37x_dbginit $_TARGETNAME + + echo "Halting target" + halt +} ###### # End Target Reset Event Setup: @@ -191,9 +200,9 @@ $_TARGETNAME configure -event \ # reset sequence. proc amdm37x_dbginit {target} { # General Cortex A8 debug initialisation - cortex_a8 dbginit - - # Enable DBGEN signal. This signal is described in the ARM v7 TRM, but + cortex_a dbginit + + # Enable DBGEN signal. This signal is described in the ARM v7 TRM, but # access to the signal appears to be implementation specific. TI does not # describe this register much except a quick line that states DBGEM (sic) is # at this address and this bit.