X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Far71xx.cfg;h=196b048685c77df1f77007d00b95faaee33885d6;hp=3ac61d94638c855382f804bb6f2ee9f4310870d6;hb=4517bcbd354206e2a9d132f80919617181059953;hpb=383a835bcd6ea6797fbf646a5faae3997b91c7e1

diff --git a/tcl/target/ar71xx.cfg b/tcl/target/ar71xx.cfg
index 3ac61d9463..196b048685 100644
--- a/tcl/target/ar71xx.cfg
+++ b/tcl/target/ar71xx.cfg
@@ -10,10 +10,10 @@ set CHIPNAME ar71xx
 
 jtag newtap $CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id 1
 
-set TARGETNAME $CHIPNAME.cpu
-target create $TARGETNAME mips_m4k -endian big -chain-position $TARGETNAME
+set _TARGETNAME $CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
 
-$TARGETNAME configure -event reset-halt-post {
+$_TARGETNAME configure -event reset-halt-post {
 	#setup PLL to lowest common denominator 300/300/150 setting
 	mww 0xb8050000 0x000f40a3	;# reset val + CPU:3 DDR:3 AHB:0
 	mww 0xb8050000 0x800f40a3	;# send to PLL
@@ -22,7 +22,7 @@ $TARGETNAME configure -event reset-halt-post {
 	mww 0xb8050008 3		;# set reset_switch and clock_switch (resets SoC)
 }
 
-$TARGETNAME configure -event reset-init {
+$_TARGETNAME configure -event reset-init {
 	#complete pll initialization
 	mww 0xb8050000 0x800f0080	;# set sw_update bit
 	mww 0xb8050008 0		;# clear reset_switch bit
@@ -50,7 +50,7 @@ $TARGETNAME configure -event reset-init {
 }
 
 # setup working area somewhere in RAM
-$TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000
+$_TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000
 
 # serial SPI capable flash
 # flash bank <driver> <base> <size> <chip_width> <bus_width>