X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fatsamv.cfg;h=43962de31a357d3f07f8ddcedd186c7761557349;hp=d1f8454d52498f1d3422168b18550ff18874d968;hb=2ed21488cd52eb8eac10b7984096bdf0652cbae7;hpb=2231da8ec4e7d7ae9b652f3dd1a7104f5a110f3f;ds=sidebyside

diff --git a/tcl/target/atsamv.cfg b/tcl/target/atsamv.cfg
index d1f8454d52..43962de31a 100644
--- a/tcl/target/atsamv.cfg
+++ b/tcl/target/atsamv.cfg
@@ -45,6 +45,14 @@ if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
    # perform a soft reset
    cortex_m reset_config sysresetreq
+
+   # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
+   # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
+   # makes the data access cacheable. This allows reading and writing data in the
+   # CPU cache from the debugger, which is far more useful than going straight to
+   # RAM when operating on typical variables, and is generally no worse when
+   # operating on special memory locations.
+   $_CHIPNAME.dap apcsw 0x08000000 0x08000000
 }
 
 set _FLASHNAME $_CHIPNAME.flash