X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fc100helper.tcl;h=32510660ee41ae837d309c28fcf3740e466db00f;hp=965887131e7b5515d4c201a8cccb6272a582b8ef;hb=edefee988045558d5d306453ce352dc06bcb7a03;hpb=a65e75ea34153a8d0a0fe0b07497ad75c5726ab6

diff --git a/tcl/target/c100helper.tcl b/tcl/target/c100helper.tcl
index 965887131e..32510660ee 100644
--- a/tcl/target/c100helper.tcl
+++ b/tcl/target/c100helper.tcl
@@ -25,18 +25,12 @@ proc helpC100 {} {
     puts "22) flashUBOOT:        will prgram NOR sectors 0-3 with u-boot.bin"
 }
 
-# mrw,mmw from davinci.cfg
-# mrw: "memory read word", returns value of $reg
-proc mrw {reg} {
-    set value ""
-    ocd_mem2array value 32 $reg 1
-    return $value(0)
-}
+source [find mem_helper.tcl]
 
 # read a 64-bit register (memory mapped)
 proc mr64bit {reg} {
     set value ""
-    ocd_mem2array value 32 $reg 2
+    mem2array value 32 $reg 2
     return $value
 }
 
@@ -50,14 +44,6 @@ proc mw64bit {reg value} {
     mww [expr $reg+4] $high
 }
 
-# mmw: "memory modify word", updates value of $reg
-#	$reg <== ((value & ~$clearbits) | $setbits)
-proc mmw {reg setbits clearbits} {
-    set old [mrw $reg]
-    set new [expr ($old & ~$clearbits) | $setbits]
-    mww $reg $new
-}
-
 
 proc showNOR {} {
     puts "This is the current NOR setup"
@@ -131,7 +117,7 @@ proc showAmbaClk {} {
     set PLL_CLK_BYPASS	             [regs PLL_CLK_BYPASS]
 
     puts [format "CLKCORE_AHB_CLK_CNTRL       (0x%x): 0x%x" $CLKCORE_AHB_CLK_CNTRL [mrw $CLKCORE_AHB_CLK_CNTRL]]
-    ocd_mem2array value 32 $CLKCORE_AHB_CLK_CNTRL 1
+    mem2array value 32 $CLKCORE_AHB_CLK_CNTRL 1
     # see if the PLL is in bypass mode
     set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ]
     puts [format "PLL bypass bit: %d" $bypass]
@@ -206,7 +192,7 @@ proc showArmClk {} {
     set PLL_CLK_BYPASS	        [regs PLL_CLK_BYPASS]
 
     puts [format "CLKCORE_ARM_CLK_CNTRL       (0x%x): 0x%x" $CLKCORE_ARM_CLK_CNTRL [mrw $CLKCORE_ARM_CLK_CNTRL]]
-    ocd_mem2array value 32 $CLKCORE_ARM_CLK_CNTRL 1
+    mem2array value 32 $CLKCORE_ARM_CLK_CNTRL 1
     # see if the PLL is in bypass mode
     set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ]
     puts [format "PLL bypass bit: %d" $bypass]
@@ -325,7 +311,7 @@ proc setupDDR2 {} {
     if {$tmp == "128M"} {
 	configureDDR2regs_128M
     } elseif {$tmp == "256M"} {
-	configureDDR2regs_256B
+	configureDDR2regs_256M
     } else {
 	puts "Don't know how to configure DDR2 setup?"
     }
@@ -469,11 +455,12 @@ proc initC100 {} {
     mww $INTC_ARM1_CONTROL_REG 0x1
     # configure clocks
     setupPLL
+    # setupUART0 must be run before setupDDR2 as setupDDR2 uses UART.
+    setupUART0
     # enable cache
     # ? (u-boot does nothing here)
     # DDR2 memory init
     setupDDR2
-    setupUART0
     putsUART0 "C100 initialization complete.\n"
     puts "C100 initialization complete."
 }
@@ -504,7 +491,7 @@ proc reboot {} {
     mww $TIMER_WDT_HIGH_BOUND  0xffffff
     mww $TIMER_WDT_CURRENT_COUNT 0x0
     puts "JTAG speed lowered to 100kHz"
-    jtag_khz 100
+    adapter_khz 100
     mww $TIMER_WDT_CONTROL 0x1
     # wait until the reset
     puts -nonewline "Wating for watchdog to trigger..."