X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Ficepick.cfg;h=a945bea8a155e324487dc8aaa8df7142bb3b962f;hp=abd7b6a084db6c5468edc49db3acffcaf97241c1;hb=d2fb461621dc97a611e7bb44a2a64e1efe300875;hpb=b1f3e89970f352d5b340f80a216dcef65691bc58

diff --git a/tcl/target/icepick.cfg b/tcl/target/icepick.cfg
index abd7b6a084..a945bea8a1 100644
--- a/tcl/target/icepick.cfg
+++ b/tcl/target/icepick.cfg
@@ -63,7 +63,8 @@ proc icepick_c_router {jrc rw block register payload} {
 	irscan $jrc [CONST IR_ROUTER] -endstate IRPAUSE
 
 	# ROUTER instructions are 32 bits wide
-	set old_dr_value [drscan $jrc 32 $new_dr_value -endstate DRPAUSE]
+	set old_dr_value 0x[drscan $jrc 32 $new_dr_value -endstate DRPAUSE]
+#	echo "\tOld router value:\t0x[format %x $old_dr_value]"
 }
 
 # Configure the icepick control register
@@ -89,18 +90,18 @@ proc icepick_c_tapenable {jrc port} {
 	# And never to enter RESET, which will disable the TAPs.
 
 	# first enable power and clock for TAP
-	icepick_c_router $jrc 1 0x2 $port 0x100048
+	icepick_c_router $jrc 1 0x2 $port 0x110048
 
 	# TRM states that the register should be read back here, skipped for now
 
 	# enable debug "default" mode
-	icepick_c_router $jrc 1 0x2 $port 0x102048
+	icepick_c_router $jrc 1 0x2 $port 0x112048
 
 	# TRM states that debug enable and debug mode should be read back and
 	# confirmed - skipped for now
 
 	# Finally select the tap
-	icepick_c_router $jrc 1 0x2 $port 0x102148
+	icepick_c_router $jrc 1 0x2 $port 0x112148
 
 	# Enter the bypass state
 	irscan $jrc [CONST IR_BYPASS] -endstate RUN/IDLE
@@ -109,15 +110,15 @@ proc icepick_c_tapenable {jrc port} {
 
 # jrc	== TAP name for the ICEpick
 # coreid== core id number 0..15 (not same as port number!)
-proc icepick_d_set_coreid {jrc coreid } {
-	icepick_c_router $jrc 1 0x6 $coreid 0x2008
+proc icepick_d_set_core_control {jrc coreid value } {
+	icepick_c_router $jrc 1 0x6 $coreid $value
 }
 
 # jrc	== TAP name for the ICEpick
 # port	== a port number, 0..15
 # Follow the sequence described in
 # http://processors.wiki.ti.com/images/f/f6/Router_Scan_Sequence-ICEpick-D.pdf
-proc icepick_d_tapenable {jrc port coreid} {
+proc icepick_d_tapenable {jrc port coreid { value 0x2008 } } {
 	# First CONNECT to the ICEPick
 	icepick_c_connect $jrc
 	icepick_c_setup $jrc
@@ -125,8 +126,8 @@ proc icepick_d_tapenable {jrc port coreid} {
 	# Select the port
 	icepick_c_router $jrc 1 0x2 $port 0x2108
 
-	# Set 4 bit core ID to the Cortex-A
-	icepick_d_set_coreid $jrc $coreid
+	# Set icepick core control for $coreid
+	icepick_d_set_core_control $jrc $coreid $value
 
 	# Enter the bypass state
 	irscan $jrc [CONST IF_BYPASS] -endstate RUN/IDLE