X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fimx51.cfg;h=d10cf9f5d5b2da3df6bb1ecd3f3fc484696a8a2d;hp=b1390ec2ef428117e02179b1534e5ed7d24decf5;hb=a0a504569b5ae4d6e485414c43be0fd4bb216bab;hpb=d5b9c7998c43ee783c224035002cf32f062b0e2b diff --git a/tcl/target/imx51.cfg b/tcl/target/imx51.cfg index b1390ec2ef..d10cf9f5d5 100644 --- a/tcl/target/imx51.cfg +++ b/tcl/target/imx51.cfg @@ -1,13 +1,13 @@ # Freescale i.MX51 if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME imx51 + set _CHIPNAME imx51 } # CoreSight Debug Access Port -if { [info exists DAP_TAPID ] } { +if { [info exists DAP_TAPID] } { set _DAP_TAPID $DAP_TAPID } else { set _DAP_TAPID 0x1ba00477 @@ -20,7 +20,7 @@ jtag newtap $_CHIPNAME DAP -irlen 4 -ircapture 0x1 -irmask 0xf \ jtag newtap $_CHIPNAME SDMA -irlen 4 -ircapture 0x0 -irmask 0xf # SJC -if { [info exists SJC_TAPID ] } { +if { [info exists SJC_TAPID] } { set _SJC_TAPID SJC_TAPID } else { set _SJC_TAPID 0x0190c01d @@ -29,23 +29,16 @@ if { [info exists SJC_TAPID ] } { jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \ -expected-id $_SJC_TAPID -ignore-version -# GDB target: Cortex-A8, using DAP +# GDB target: Cortex-A8, using DAP set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.DAP +target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.DAP # some TCK tycles are required to activate the DEBUG power domain jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100" -# have the DAP "always" be active -jtag configure $_CHIPNAME.SJC -event setup "jtag tapenable $_CHIPNAME.DAP" - proc imx51_dbginit {target} { - # General Cortex A8 debug initialisation - cortex_a8 dbginit + # General Cortex-A8 debug initialisation + cortex_a dbginit } -# Slow speed to be sure it will work -jtag_rclk 1000 -$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 } - $_TARGETNAME configure -event reset-assert-post "imx51_dbginit $_TARGETNAME"