X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fimx8m.cfg;h=9a8bfecb1c667be20c4e156567aa9bc0b43dc517;hp=33149540af176ea5e5ded31960764f327c5d8979;hb=78c87f5e81f8b3ee2a72aa546f87985596cb2b9f;hpb=c0f81fbee745e34d04d490df0b26d8e443d90c0e

diff --git a/tcl/target/imx8m.cfg b/tcl/target/imx8m.cfg
index 33149540af..9a8bfecb1c 100644
--- a/tcl/target/imx8m.cfg
+++ b/tcl/target/imx8m.cfg
@@ -35,7 +35,7 @@ set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
 for { set _core 0 } { $_core < $_cores } { incr _core } {
 
     cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \
-        -ctibase [lindex $CTIBASE $_core]
+        -baseaddr [lindex $CTIBASE $_core]
 
     set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
         -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core"
@@ -52,4 +52,13 @@ for { set _core 0 } { $_core < $_cores } { incr _core } {
 }
 
 eval $_smp_command
+
+# declare the auxiliary Cortex-M4 core on AP #4
+target create ${_CHIPNAME}.m4 cortex_m -dap ${_CHIPNAME}.dap -ap-num 4 \
+               -defer-examine
+
+# AHB-AP for direct access to soc bus
+target create ${_CHIPNAME}.ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 0
+
+# default target is A53 core 0
 targets $_TARGETNAME.0