X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fixp42x.cfg;h=ee10b2157cf8bf5e9a0b9669f404e012489f9ab9;hp=6e5857a57e36f8868ddc197f04c1389a25fda87c;hb=78c87f5e81f8b3ee2a72aa546f87985596cb2b9f;hpb=23bf724e048df62181e744245af42d3694989749

diff --git a/tcl/target/ixp42x.cfg b/tcl/target/ixp42x.cfg
index 6e5857a57e..ee10b2157c 100644
--- a/tcl/target/ixp42x.cfg
+++ b/tcl/target/ixp42x.cfg
@@ -1,19 +1,19 @@
 #xscale ixp42x CPU
 
 if { [info exists CHIPNAME] } {
-   set  _CHIPNAME $CHIPNAME
+   set _CHIPNAME $CHIPNAME
 } else {
-   set  _CHIPNAME ixp42x
+   set _CHIPNAME ixp42x
 }
 
 if { [info exists ENDIAN] } {
-   set  _ENDIAN $ENDIAN
+   set _ENDIAN $ENDIAN
 } else {
   # this defaults to a bigendian
-   set  _ENDIAN big
+   set _ENDIAN big
 }
 
-if { [info exists CPUTAPID ] } {
+if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
    set _CPUTAPID 0x19274013
@@ -27,7 +27,7 @@ set _CPUTAPID6 0x29277013
 jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID -expected-id $_CPUTAPID2 -expected-id $_CPUTAPID3 -expected-id $_CPUTAPID4 -expected-id $_CPUTAPID5 -expected-id $_CPUTAPID6
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant ixp42x
+target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME
 
 
 # register constants for IXP42x SDRAM controller
@@ -36,21 +36,21 @@ global IXP425_SDRAM_IR_MODE_SET_CAS3_CMD
 set IXP425_SDRAM_IR_MODE_SET_CAS2_CMD	0x0000
 set IXP425_SDRAM_IR_MODE_SET_CAS3_CMD	0x0001
 
-global IXP42x_SDRAM_CL3			
-global IXP42x_SDRAM_CL2			
+global IXP42x_SDRAM_CL3
+global IXP42x_SDRAM_CL2
 set IXP42x_SDRAM_CL3			0x0008
 set IXP42x_SDRAM_CL2			0x0000
 
-global IXP42x_SDRAM_8MB_2Mx32_1BANK	
-global IXP42x_SDRAM_16MB_2Mx32_2BANK	
-global IXP42x_SDRAM_16MB_4Mx16_1BANK	
-global IXP42x_SDRAM_32MB_4Mx16_2BANK	
-global IXP42x_SDRAM_32MB_8Mx16_1BANK	
-global IXP42x_SDRAM_64MB_8Mx16_2BANK	
-global IXP42x_SDRAM_64MB_16Mx16_1BANK	
-global IXP42x_SDRAM_128MB_16Mx16_2BANK	
-global IXP42x_SDRAM_128MB_32Mx16_1BANK	
-global IXP42x_SDRAM_256MB_32Mx16_2BANK	
+global IXP42x_SDRAM_8MB_2Mx32_1BANK
+global IXP42x_SDRAM_16MB_2Mx32_2BANK
+global IXP42x_SDRAM_16MB_4Mx16_1BANK
+global IXP42x_SDRAM_32MB_4Mx16_2BANK
+global IXP42x_SDRAM_32MB_8Mx16_1BANK
+global IXP42x_SDRAM_64MB_8Mx16_2BANK
+global IXP42x_SDRAM_64MB_16Mx16_1BANK
+global IXP42x_SDRAM_128MB_16Mx16_2BANK
+global IXP42x_SDRAM_128MB_32Mx16_1BANK
+global IXP42x_SDRAM_256MB_32Mx16_2BANK
 
 set IXP42x_SDRAM_8MB_2Mx32_1BANK	0x0030
 set IXP42x_SDRAM_16MB_2Mx32_2BANK	0x0031
@@ -66,18 +66,18 @@ set IXP42x_SDRAM_256MB_32Mx16_2BANK	0x0015
 
 # helper function to init SDRAM on IXP42x.
 # SDRAM_CFG: one of IXP42X_SDRAM_xxx
-# REFRESH: refresh counter reload value (integer) 
-# CASLAT: 2 or 3 
+# REFRESH: refresh counter reload value (integer)
+# CASLAT: 2 or 3
 proc ixp42x_init_sdram { SDRAM_CFG REFRESH CASLAT } {
 
     switch $CASLAT {
-	2 { 
-	    set SDRAM_CFG [expr $SDRAM_CFG | $::IXP42x_SDRAM_CL2 ] 
-	    set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS2_CMD 
+	2 {
+	    set SDRAM_CFG [expr {$SDRAM_CFG | $::IXP42x_SDRAM_CL2} ]
+	    set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS2_CMD
 	}
 	3 {
-	    set SDRAM_CFG [expr $SDRAM_CFG | $::IXP42x_SDRAM_CL3 ] 
-	    set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS3_CMD 
+	    set SDRAM_CFG [expr {$SDRAM_CFG | $::IXP42x_SDRAM_CL3} ]
+	    set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS3_CMD
 	}
 	default { error [format "unsupported cas latency \"%s\" " $CASLAT] }
     }
@@ -104,4 +104,3 @@ proc ixp42x_init_sdram { SDRAM_CFG REFRESH CASLAT } {
 proc ixp42x_set_bigendian { } {
     reg XSCALE_CTRL 0xF8
 }
-