X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Flpc1768.cfg;fp=tcl%2Ftarget%2Flpc1768.cfg;h=0000000000000000000000000000000000000000;hp=a436b30f69bbdee7b6bbb7257d909790eb0ece51;hb=b5a6ba46aaed530a4b1397b9617de0ff316f6efb;hpb=1e439e2a9a4392586bdfce0ebab4d63690f7fe6e

diff --git a/tcl/target/lpc1768.cfg b/tcl/target/lpc1768.cfg
deleted file mode 100644
index a436b30f69..0000000000
--- a/tcl/target/lpc1768.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
-set CHIPNAME lpc1768
-set CPUTAPID 0x4ba00477
-set CPURAMSIZE 0x8000
-set CPUROMSIZE 0x80000
-
-# After reset the chip is clocked by the ~4MHz internal RC oscillator.
-# When board-specific code (reset-init handler or device firmware)
-# configures another oscillator and/or PLL0, set CCLK to match; if
-# you don't, then flash erase and write operations may misbehave.
-# (The ROM code doing those updates cares about core clock speed...)
-#
-# CCLK is the core clock frequency in KHz
-set CCLK 4000
-
-#Include the main configuration file.
-source [find target/lpc17xx.cfg];