X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Flpc4350.cfg;h=47f252963a16975995d3af251fb2ba1e772885e3;hp=fbbea97d7ff802ab602ec88cacd973b056e99843;hb=b7d2cdc0d4fc319169c60362708a67e2ff626525;hpb=564a5eb5375aa8117ee4fe48899f07490da8ae8a

diff --git a/tcl/target/lpc4350.cfg b/tcl/target/lpc4350.cfg
index fbbea97d7f..47f252963a 100644
--- a/tcl/target/lpc4350.cfg
+++ b/tcl/target/lpc4350.cfg
@@ -40,12 +40,12 @@ jtag newtap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
 jtag newtap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
 				-expected-id $_M0_JTAG_TAPID
 
-target create $_CHIPNAME.m4 cortex_m3 -chain-position $_CHIPNAME.m4
-target create $_CHIPNAME.m0 cortex_m3 -chain-position $_CHIPNAME.m0
+target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4
+target create $_CHIPNAME.m0 cortex_m -chain-position $_CHIPNAME.m0
 
 # on this CPU we should use VECTRESET to perform a soft reset and
 # manually reset the periphery
 # SRST or SYSRESETREQ disable the debug interface for the time of
 # the reset and will not fit our requirements for a consistent debug
 # session
-cortex_m3 reset_config vectreset
+cortex_m reset_config vectreset