X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Flpc4370.cfg;h=fe9e76b7a1c8fcf561ad530d261a0203e0a98702;hp=67bff0adcacd47722d35b6de030454ac3e42b9b5;hb=HEAD;hpb=fad64c618025ea96be585b0900bd70c2e5a8713a

diff --git a/tcl/target/lpc4370.cfg b/tcl/target/lpc4370.cfg
index 67bff0adca..fe9e76b7a1 100644
--- a/tcl/target/lpc4370.cfg
+++ b/tcl/target/lpc4370.cfg
@@ -1,8 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # NXP LPC4370 - 1x ARM Cortex-M4 + 2x ARM Cortex-M0 @ up to 204 MHz each
 #
 
-adapter_khz 500
+adapter speed 500
 
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $CHIPNAME
@@ -47,8 +49,8 @@ if { [info exists M0_JTAG_TAPID] } {
 
 swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
 				-expected-id $_M4_TAPID
-
-target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4
+dap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4
+target create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap
 
 # LPC4370 has 96+32 KB contiguous SRAM
 if { [info exists WORKAREASIZE] } {
@@ -65,8 +67,10 @@ if { [using_jtag] } {
 	jtag newtap $_CHIPNAME m0sub -irlen 4 -ircapture 0x1 -irmask 0xf \
 					-expected-id $_M0_JTAG_TAPID
 
-	target create $_CHIPNAME.m0app cortex_m -chain-position $_CHIPNAME.m0app
-	target create $_CHIPNAME.m0sub cortex_m -chain-position $_CHIPNAME.m0sub
+	dap create $_CHIPNAME.m0app.dap -chain-position $_CHIPNAME.m0app
+	dap create $_CHIPNAME.m0sub.dap -chain-position $_CHIPNAME.m0sub
+	target create $_CHIPNAME.m0app cortex_m -dap $_CHIPNAME.m0app.dap
+	target create $_CHIPNAME.m0sub cortex_m -dap $_CHIPNAME.m0sub.dap
 
 	# 32+8+32 KB SRAM
 	$_CHIPNAME.m0app configure -work-area-phys 0x10080000 \