X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fnrf52.cfg;h=d0c52fdabce7959426fe1f0515123f55eacf5a71;hp=88f2c6912a8c380b47534ff7e5183ca20351b219;hb=HEAD;hpb=73a5f58adba73306b08b7bb22ff8a9511e79869f

diff --git a/tcl/target/nrf52.cfg b/tcl/target/nrf52.cfg
index 88f2c6912a..0c82c5758a 100644
--- a/tcl/target/nrf52.cfg
+++ b/tcl/target/nrf52.cfg
@@ -1,8 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Nordic nRF52 series: ARM Cortex-M4 @ 64 MHz
 #
 
 source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
 
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $CHIPNAME
@@ -53,7 +56,7 @@ flash bank $_CHIPNAME.uicr nrf5 0x10001000 0 1 1 $_TARGETNAME
 # Test if MEM-AP is locked by UICR APPROTECT
 proc nrf52_check_ap_lock {} {
 	set dap [[target current] cget -dap]
-	set err [catch {set APPROTECTSTATUS [ocd_$dap apreg 1 0xc]}]
+	set err [catch {set APPROTECTSTATUS [$dap apreg 1 0xc]}]
 	if {$err == 0 && $APPROTECTSTATUS != 1} {
 		echo "****** WARNING ******"
 		echo "nRF52 device has AP lock engaged (see UICR APPROTECT register)."
@@ -71,7 +74,7 @@ proc nrf52_recover {} {
 	set target [target current]
 	set dap [$target cget -dap]
 
-	set IDR [ocd_$dap apreg 1 0xfc]
+	set IDR [$dap apreg 1 0xfc]
 	if {$IDR != 0x02880000} {
 		echo "Error: Cannot access nRF52 CTRL-AP!"
 		return
@@ -79,37 +82,86 @@ proc nrf52_recover {} {
 
 	poll off
 
-	# Assert reset
-	$dap apreg 1 0 1
-
-	# Reset ERASEALLSTATUS event
-	$dap apreg 1 8 0
-
-	# Trigger ERASEALL task
+	# Reset and trigger ERASEALL task
 	$dap apreg 1 4 0
 	$dap apreg 1 4 1
 
 	for {set i 0} {1} {incr i} {
-		set ERASEALLSTATUS [ocd_$dap apreg 1 8]
-		if {$ERASEALLSTATUS == 1} {
+		set ERASEALLSTATUS [$dap apreg 1 8]
+		if {$ERASEALLSTATUS == 0} {
 			echo "$target device has been successfully erased and unlocked."
 			break
 		}
-		if {$i >= 5} {
+		if {$i == 0} {
+			echo "Waiting for chip erase..."
+		}
+		if {$i >= 150} {
 			echo "Error: $target recovery failed."
 			break
 		}
 		sleep 100
 	}
 
+	# Assert reset
+	$dap apreg 1 0 1
+
 	# Deassert reset
 	$dap apreg 1 0 0
 
-	if {$ERASEALLSTATUS == 1} {
-		sleep 100
-		$target arp_examine
-		poll on
-	}
+	# Reset ERASEALL task
+	$dap apreg 1 4 0
+
+	sleep 100
+	$target arp_examine
+	poll on
 }
 
 add_help_text nrf52_recover "Mass erase and unlock nRF52 device"
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname _chipname} {
+	targets $_targetname
+
+	# Read FICR.INFO.PART
+	set PART [mrw 0x10000100]
+
+	switch $PART {
+		0x52840 -
+		0x52833 -
+		0x52832 {
+			if { [$_chipname.tpiu cget -protocol] eq "sync" } {
+				if { [$_chipname.tpiu cget -port-width] != 4 } {
+					echo "Error. Device only supports 4-bit sync traces."
+					return
+				}
+
+				# Set TRACECONFIG.TRACEMUX to enable synchronous trace
+				mmw 0x4000055C 0x00020000 0x00010000
+				$_targetname configure -event reset-end {
+					mmw 0x4000055C 0x00020000 0x00010000
+				}
+			} else {
+				# Set TRACECONFIG.TRACEMUX to enable SWO
+				mmw 0x4000055C 0x00010000 0x00020000
+				$_targetname configure -event reset-end {
+					mmw 0x4000055C 0x00010000 0x00020000
+				}
+			}
+		}
+		0x52820 -
+		0x52811 -
+		0x52810 -
+		0x52805 {
+			echo "Error: Device does not support TPIU"
+			return
+		}
+		default {
+			echo "Error: Unknown device"
+			return
+		}
+	}
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME $_CHIPNAME"