X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fomap3530.cfg;fp=tcl%2Ftarget%2Fomap3530.cfg;h=dcf7c513958617cbabfd3859abeddfce218c3332;hp=078d7f24db97b3a431e8a7d8ba8b226bca019d3a;hb=38ac08c1c25adf42cf20e48e10e6ddeab6a12d71;hpb=0d598535a30ea553f5a5d4a0047010807fcc5996

diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg
index 078d7f24db..dcf7c51395 100644
--- a/tcl/target/omap3530.cfg
+++ b/tcl/target/omap3530.cfg
@@ -63,8 +63,8 @@ proc omap3_dbginit {target} {
 # be absolutely certain the JTAG clock will work with the worst-case
 # 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
 # OK to speed up *after* PLL and clock tree setup.
-adapter_khz 1000
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1000 }
+adapter speed 1000
+$_TARGETNAME configure -event "reset-start" { adapter speed 1000 }
 
 # Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
 # ourselves using PRM_RSTCTRL.  RST_GS (2) is a warm reset, like ICEpick