X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fomap3530.cfg;h=0e20852ca12d499bbd9b851d6b8078e9a75fef0f;hp=ad8f8ea8c53dd8b593fccb135dfd0b0972e5e7c4;hb=d9ba56c295f057e716519a798bf9cdb4898c24f4;hpb=dbbc9c41f7db210b0a4e226540a28e0a8a5019bf

diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg
index ad8f8ea8c5..0e20852ca1 100644
--- a/tcl/target/omap3530.cfg
+++ b/tcl/target/omap3530.cfg
@@ -1,57 +1,74 @@
-#File omap3530.cfg - as found on the BEAGLEBOARD
-#  Assumption is it is generic for all OMAP3530 
+# TI OMAP3530
+# http://focus.ti.com/docs/prod/folders/print/omap3530.html
+# Other OMAP3 chips remove DSP and/or the OpenGL support
 
-#TI OMAP3 processor - http://www.ti.com 
-
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
-   set  _CHIPNAME omap3
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME omap3530
 }
 
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
-  # this defaults to a little endianness
-  set  _ENDIAN little
-}
+# ICEpick-C ... used to route Cortex, DSP, and more not shown here
+source [find target/icepick.cfg]
+
+# Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
+jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
 
-if { [info exists CPUTAPID ] } {
-   set _CPUTAPID $CPUTAPID
+# Subsidiary TAP: CoreSight Debug Access Port (DAP)
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
 } else {
-  # force an error till we get a good number
-  set _CPUTAPID 0x0B6D602F
+   set _DAP_TAPID 0x0b6d602f
 }
+jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
+	-expected-id $_DAP_TAPID -disable
+jtag configure $_CHIPNAME.dap -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 3"
 
-#jtag scan chain
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0 -expected-id $_CPUTAPID -disable
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0xf -expected-id 0x0b7ae02f
-
-target create omap3.cpu cortex_m3 -endian little -chain-position omap3.cpu
-
-jtag configure $_CHIPNAME.cpu -event tap-enable {
-	puts "Enabling Cortex-A8 @ OMAP3"
-	irscan omap3.jrc 7 -endstate IRPAUSE
-	drscan omap3.jrc 8 0x89 -endstate DRPAUSE
-	irscan omap3.jrc 2 -endstate IRPAUSE
-	drscan omap3.jrc 32 0xa3002108  -endstate RUN/IDLE
-	irscan omap3.jrc 0x3F -endstate RUN/IDLE
-	runtest 10
-	puts "Cortex-A8 @ OMAP3 enabled"
+# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
+if { [info exists JRC_TAPID] } {
+   set _JRC_TAPID $JRC_TAPID
+} else {
+   set _JRC_TAPID 0x0b7ae02f
 }
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
+	-expected-id $_JRC_TAPID
+
+# GDB target: Cortex-A8, using DAP
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
+
+# SRAM: 64K at 0x4020.0000; use the first 16K
+$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
 
-proc omap3_dbginit { } {
-     version
-     jtag tapenable omap3.cpu
-     targets
-     # sleep 1000
-     # dap apsel 1
-     # sleep 1000
-     # dap apsel 1
-     # dap info 1
-     omap3.cpu mww 0x54011FB0 0xC5ACCE55 4
-     omap3.cpu mdw 0x54011314
-     omap3.cpu mdw 0x54011314
-     # omap3.cpu mdw 0x54011080
-     omap3.cpu mww 0x5401d030 0x00002000 4
+###################
+
+# the reset sequence is event-driven
+# and kind of finicky...
+
+# some TCK tycles are required to activate the DEBUG power domain
+jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
+
+# have the DAP "always" be active
+jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
+
+proc omap3_dbginit {target} {
+     # General Cortex A8 debug initialisation
+     cortex_a dbginit
+     # Enable DBGU signal for OMAP353x
+     $target mww phys 0x5401d030 0x00002000
 }
+
+# be absolutely certain the JTAG clock will work with the worst-case
+# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
+# OK to speed up *after* PLL and clock tree setup.
+jtag_rclk 1000
+$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
+
+# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
+# ourselves using PRM_RSTCTRL.  RST_GS (2) is a warm reset, like ICEpick
+# would issue.  RST_DPLL3 (4) is a cold reset.
+set PRM_RSTCTRL 0x48307250
+$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww $PRM_RSTCTRL 2"
+
+$_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME"