X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fomap4430.cfg;h=a448550f679b375e5f4c8619e16e724374b2e7be;hp=2e9f5543bc15d459ca0c207d56fc57a4ae8297a0;hb=HEAD;hpb=b7d2cdc0d4fc319169c60362708a67e2ff626525

diff --git a/tcl/target/omap4430.cfg b/tcl/target/omap4430.cfg
index 2e9f5543bc..a448550f67 100644
--- a/tcl/target/omap4430.cfg
+++ b/tcl/target/omap4430.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # OMAP4430
 
 if { [info exists CHIPNAME] } {
@@ -22,9 +24,9 @@ if { [info exists DAP_TAPID] } {
 	set _DAP_TAPID 0x3BA00477
 }
 
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
 	-expected-id $_DAP_TAPID -disable
-jtag configure $_CHIPNAME.dap -event tap-enable \
+jtag configure $_CHIPNAME.cpu -event tap-enable \
 	"icepick_c_tapenable $_CHIPNAME.jrc 9"
 
 
@@ -37,14 +39,14 @@ if { [info exists M3_DAP_TAPID] } {
 	set _M3_DAP_TAPID 0x4BA00477
 }
 
-jtag newtap $_CHIPNAME m31_dap -irlen 4 -ircapture 0x1 -irmask 0xf \
+jtag newtap $_CHIPNAME m31 -irlen 4 -ircapture 0x1 -irmask 0xf \
 	-expected-id $_M3_DAP_TAPID -disable
-jtag configure $_CHIPNAME.m31_dap -event tap-enable \
+jtag configure $_CHIPNAME.m31 -event tap-enable \
 	"icepick_c_tapenable $_CHIPNAME.jrc 5"
 
-jtag newtap $_CHIPNAME m30_dap -irlen 4 -ircapture 0x1 -irmask 0xf \
+jtag newtap $_CHIPNAME m30 -irlen 4 -ircapture 0x1 -irmask 0xf \
 	-expected-id $_M3_DAP_TAPID -disable
-jtag configure $_CHIPNAME.m30_dap -event tap-enable \
+jtag configure $_CHIPNAME.m30 -event tap-enable \
 	"icepick_c_tapenable $_CHIPNAME.jrc 4"
 
 
@@ -91,10 +93,11 @@ set _TARGETNAME $_CHIPNAME.cpu
 # 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT)
 
 set _coreid 0
-set _dbgbase [expr 0x80000000 | ($_coreid << 13)]
+set _dbgbase [expr {0x80000000 | ($_coreid << 13)}]
 echo "Using dbgbase = [format 0x%x $_dbgbase]"
- 
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap \
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \
   -coreid 0 -dbgbase $_dbgbase
 
 # SRAM: 56KiB at 0x4030.0000
@@ -104,15 +107,17 @@ $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
 #
 # M3 targets, separate TAP/DAP for each core
 #
-target create $_CHIPNAME.m30 cortex_m -chain-position $_CHIPNAME.m30_dap
-target create $_CHIPNAME.m31 cortex_m -chain-position $_CHIPNAME.m31_dap
+dap create $_CHIPNAME.m30_dap -chain-position $_CHIPNAME.m30
+dap create $_CHIPNAME.m31_dap -chain-position $_CHIPNAME.m31
+target create $_CHIPNAME.m30 cortex_m -dap $_CHIPNAME.m30_dap
+target create $_CHIPNAME.m31 cortex_m -dap $_CHIPNAME.m31_dap
 
 
 # Once the JRC is up, enable our TAPs
 jtag configure $_CHIPNAME.jrc -event setup "
-	jtag tapenable $_CHIPNAME.dap
-	jtag tapenable $_CHIPNAME.m30_dap
-	jtag tapenable $_CHIPNAME.m31_dap
+	jtag tapenable $_CHIPNAME.cpu
+	jtag tapenable $_CHIPNAME.m30
+	jtag tapenable $_CHIPNAME.m31
 "
 
 # Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
@@ -124,4 +129,3 @@ $_CHIPNAME.m31 configure -event reset-assert { }
 
 # Soft breakpoints don't currently work due to broken cache handling
 gdb_breakpoint_override hard
-