X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fpxa255.cfg;h=386242597cefd9b3a8ae3d59a455c67170458a62;hp=44efdaa4b9987f9d2abafae5eace0a20104fafc8;hb=79d6d3cda90c6694343bde909978069994049ab7;hpb=4a26390eec5b969c07684ab5d4b7e957011d71bd

diff --git a/tcl/target/pxa255.cfg b/tcl/target/pxa255.cfg
index 44efdaa4b9..386242597c 100644
--- a/tcl/target/pxa255.cfg
+++ b/tcl/target/pxa255.cfg
@@ -1,19 +1,19 @@
 # PXA255 chip ... originally from Intel, PXA line was sold to Marvell.
-#  This chip is now at end-of-life.  Final orders have been taken.
+# This chip is now at end-of-life.  Final orders have been taken.
 
 if { [info exists CHIPNAME] } {
-   set  _CHIPNAME $CHIPNAME
+   set _CHIPNAME $CHIPNAME
 } else {
-   set  _CHIPNAME pxa255
+   set _CHIPNAME pxa255
 }
 
 if { [info exists ENDIAN] } {
-   set  _ENDIAN $ENDIAN
+   set _ENDIAN $ENDIAN
 } else {
-   set  _ENDIAN little
+   set _ENDIAN little
 }
 
-if { [info exists CPUTAPID ] } {
+if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
    set _CPUTAPID 0x69264013
@@ -28,8 +28,8 @@ target create $_TARGETNAME xscale -endian $_ENDIAN \
 # PXA255 comes out of reset using 3.6864 MHz oscillator.
 # Until the PLL kicks in, keep the JTAG clock slow enough
 # that we get no errors.
-jtag_khz 300
-$_TARGETNAME configure -event "reset-start" { jtag_khz 300 }
+adapter_khz 300
+$_TARGETNAME configure -event "reset-start" { adapter_khz 300 }
 
 # both TRST and SRST are *required* for debug
 # DCSR is often accessed with SRST active