X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fstm32f2x.cfg;h=43a944c103d10f646e757fdf8235eb82358fdd45;hp=a3076535fa913846bbf836bdf2c7769f42e00a84;hb=b7d2cdc0d4fc319169c60362708a67e2ff626525;hpb=f0ef9960b6f4caacc69c4a839e6b759e8c6a9b82

diff --git a/tcl/target/stm32f2x.cfg b/tcl/target/stm32f2x.cfg
index a3076535fa..43a944c103 100644
--- a/tcl/target/stm32f2x.cfg
+++ b/tcl/target/stm32f2x.cfg
@@ -28,7 +28,7 @@ if { [info exists WORKAREASIZE] } {
 # that there can be a pretty wide band where things are more or less stable.
 adapter_khz 1000
 
-jtag_nsrst_delay 100
+adapter_nsrst_delay 100
 jtag_ntrst_delay 100
 
 #jtag scan chain
@@ -52,7 +52,7 @@ if { [info exists BSTAPID] } {
 jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -61,4 +61,4 @@ flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq