X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fstm32f3x.cfg;h=0c8919f1dc1ddf22822d3abbe8c66ecbf12cdb9c;hp=0b3b7255f25829f415140c69cb973bdd3958566d;hb=a0b76360b874607f2aa075e764891f129b5ff0f9;hpb=c7384117c66e8f18896ca09ab8095d6da16bb1e5

diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg
index 0b3b7255f2..0c8919f1dc 100644
--- a/tcl/target/stm32f3x.cfg
+++ b/tcl/target/stm32f3x.cfg
@@ -4,6 +4,7 @@
 # stm32 devices support both JTAG and SWD transports.
 #
 source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
@@ -11,11 +12,7 @@ if { [info exists CHIPNAME] } {
    set _CHIPNAME stm32f3x
 }
 
-if { [info exists ENDIAN] } {
-   set _ENDIAN $ENDIAN
-} else {
-   set _ENDIAN little
-}
+set _ENDIAN little
 
 # Work-area is a space in RAM used for flash programming
 # By default use 16kB
@@ -53,17 +50,8 @@ if { [info exists CPUTAPID] } {
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
-if { [info exists BSTAPID] } {
-   set _BSTAPID $BSTAPID
-} else {
-  # STM Document RM0316 rev 2 Section 30.6.2 says 0x06432041
-  # but STM32F303VCT6 rev Y has 0x06422041
-  set _BSTAPID1 0x06422041
-  set _BSTAPID2 0x06432041
-}
-
 if {[using_jtag]} {
- swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2
+   jtag newtap $_CHIPNAME bs -irlen 5
 }
 
 set _TARGETNAME $_CHIPNAME.cpu
@@ -74,8 +62,47 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
 
+reset_config srst_nogate
+
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
    # perform a soft reset
    cortex_m reset_config sysresetreq
 }
+
+proc stm32f3x_default_reset_start {} {
+	# Reset clock is HSI (8 MHz)
+	adapter_khz 1000
+}
+
+proc stm32f3x_default_examine_end {} {
+	# Enable debug during low power modes (uses more power)
+	mmw 0xe0042004 0x00000007 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+
+	# Stop watchdog counters during halt
+	mmw 0xe0042008 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+}
+
+proc stm32f3x_default_reset_init {} {
+	# Configure PLL to boost clock to HSI x 8 (64 MHz)
+	mww 0x40021004 0x00380400   ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2]
+	mmw 0x40021000 0x01000000 0 ;# RCC_CR |= PLLON
+	mww 0x40022000 0x00000012   ;# FLASH_ACR = PRFTBE | LATENCY[1]
+	sleep 10                    ;# Wait for PLL to lock
+	mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
+
+	# Boost JTAG frequency
+	adapter_khz 8000
+}
+
+# Default hooks
+$_TARGETNAME configure -event examine-end { stm32f3x_default_examine_end }
+$_TARGETNAME configure -event reset-start { stm32f3x_default_reset_start }
+$_TARGETNAME configure -event reset-init { stm32f3x_default_reset_init }
+
+$_TARGETNAME configure -event trace-config {
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xe0042004 0x00000020 0
+}