X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fstm32f3x.cfg;h=86e9f594e38053347387e33122ba7e04717e11d8;hp=1f051434611a3015cffcc2e0cd98a1995468f7b8;hb=2231da8ec4e7d7ae9b652f3dd1a7104f5a110f3f;hpb=1df6e59178d1ce7d466a1c9821a1ea88b8df3e4a

diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg
index 1f05143461..86e9f594e3 100644
--- a/tcl/target/stm32f3x.cfg
+++ b/tcl/target/stm32f3x.cfg
@@ -1,16 +1,18 @@
 # script for stm32f3x family
 
+#
+# stm32 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
 } else {
    set _CHIPNAME stm32f3x
 }
 
-if { [info exists ENDIAN] } {
-   set _ENDIAN $ENDIAN
-} else {
-   set _ENDIAN little
-}
+set _ENDIAN little
 
 # Work-area is a space in RAM used for flash programming
 # By default use 16kB
@@ -29,35 +31,79 @@ if { [info exists WORKAREASIZE] } {
 adapter_khz 1000
 
 adapter_nsrst_delay 100
-jtag_ntrst_delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
 
 #jtag scan chain
 if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
-  # See STM Document RM0316
-  # Section 29.6.3 - corresponds to Cortex-M4 r0p1
-   set _CPUTAPID 0x4ba00477
+   if { [using_jtag] } {
+      # See STM Document RM0316
+      # Section 29.6.3 - corresponds to Cortex-M4 r0p1
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
 }
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
-if { [info exists BSTAPID] } {
-   set _BSTAPID $BSTAPID
-} else {
-  # See STM Document RM0316
-  # Section 29.6.2
-  set _BSTAPID 0x06432041
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
 }
-jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
 
-# if srst is not fitted use SYSRESETREQ to
-# perform a soft reset
-cortex_m3 reset_config sysresetreq
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+proc stm32f3x_default_reset_start {} {
+	# Reset clock is HSI (8 MHz)
+	adapter_khz 1000
+}
+
+proc stm32f3x_default_examine_end {} {
+	# Enable debug during low power modes (uses more power)
+	mmw 0xe0042004 0x00000007 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+
+	# Stop watchdog counters during halt
+	mmw 0xe0042008 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+}
+
+proc stm32f3x_default_reset_init {} {
+	# Configure PLL to boost clock to HSI x 8 (64 MHz)
+	mww 0x40021004 0x00380400   ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2]
+	mmw 0x40021000 0x01000000 0 ;# RCC_CR |= PLLON
+	mww 0x40022000 0x00000012   ;# FLASH_ACR = PRFTBE | LATENCY[1]
+	sleep 10                    ;# Wait for PLL to lock
+	mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
+
+	# Boost JTAG frequency
+	adapter_khz 8000
+}
+
+# Default hooks
+$_TARGETNAME configure -event examine-end { stm32f3x_default_examine_end }
+$_TARGETNAME configure -event reset-start { stm32f3x_default_reset_start }
+$_TARGETNAME configure -event reset-init { stm32f3x_default_reset_init }
+
+$_TARGETNAME configure -event trace-config {
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xe0042004 0x00000020 0
+}