X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fstm32f3x.cfg;h=ca8e6e1d8cb9db92998c15539719d7d694e5bfc5;hp=f3c22af7ae2a9a570f7bdd938053c6976ac9c81e;hb=68921d231655be696d6aad5ca7abe26cb5f17104;hpb=a09a75653dbe7ad99da6349285ab6622b80fdc15

diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg
index f3c22af7ae..ca8e6e1d8c 100644
--- a/tcl/target/stm32f3x.cfg
+++ b/tcl/target/stm32f3x.cfg
@@ -104,11 +104,11 @@ proc stm32f3x_default_examine_end {} {
 
 proc stm32f3x_default_reset_init {} {
 	# Configure PLL to boost clock to HSI x 8 (64 MHz)
-	mww 0x40021004 0x00380400 ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2]
-	mwh 0x40021002 0x0100     ;# RCC_CR[31:16] = PLLON
-	mww 0x40022000 0x00000012 ;# FLASH_ACR = PRFTBE | LATENCY[1]
-	sleep 10                  ;# Wait for PLL to lock
-	mww 0x40021004 0x00380402 ;# RCC_CFGR |= SW[1]
+	mww 0x40021004 0x00380400   ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2]
+	mmw 0x40021000 0x01000000 0 ;# RCC_CR |= PLLON
+	mww 0x40022000 0x00000012   ;# FLASH_ACR = PRFTBE | LATENCY[1]
+	sleep 10                    ;# Wait for PLL to lock
+	mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
 
 	# Boost JTAG frequency
 	adapter_khz 8000