X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fstm32f7x.cfg;h=b0468e21e13c781a76029e8cc8154b8d59dc785f;hp=e06a34594f45040ea4e72ffb85dbffc4852e90d1;hb=2ed21488cd52eb8eac10b7984096bdf0652cbae7;hpb=da4b2d5beb5ff19af8099d15f6a44513703f355c

diff --git a/tcl/target/stm32f7x.cfg b/tcl/target/stm32f7x.cfg
index e06a34594f..b0468e21e1 100755
--- a/tcl/target/stm32f7x.cfg
+++ b/tcl/target/stm32f7x.cfg
@@ -65,6 +65,14 @@ if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
    # perform a soft reset
    cortex_m reset_config sysresetreq
+
+   # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
+   # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
+   # makes the data access cacheable. This allows reading and writing data in the
+   # CPU cache from the debugger, which is far more useful than going straight to
+   # RAM when operating on typical variables, and is generally no worse when
+   # operating on special memory locations.
+   $_CHIPNAME.dap apcsw 0x08000000 0x08000000
 }
 
 $_TARGETNAME configure -event examine-end {
@@ -146,10 +154,3 @@ $_TARGETNAME configure -event reset-start {
 	adapter_khz 2000
 }
 
-# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
-# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
-# makes the data access cacheable. This allows reading and writing data in the
-# CPU cache from the debugger, which is far more useful than going straight to
-# RAM when operating on typical variables, and is generally no worse when
-# operating on special memory locations.
-$_CHIPNAME.dap apcsw 0x08000000 0x08000000