X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fstm32h7x.cfg;h=ca685c2f27e3863b2a415691e2256290ee44a9ca;hp=763a7857a08cb6cffc104658d93805a66b7dc9f7;hb=78c87f5e81f8b3ee2a72aa546f87985596cb2b9f;hpb=535f5309ba1277479d44f471655bf722e32fbb6b

diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg
index 763a7857a0..ca685c2f27 100644
--- a/tcl/target/stm32h7x.cfg
+++ b/tcl/target/stm32h7x.cfg
@@ -77,6 +77,8 @@ if {![using_hla]} {
 	# STM32H7 provides an APB-AP at access port 2, which allows the access to
 	# the debug and trace features on the system APB System Debug Bus (APB-D).
 	target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
+	swo  create $_CHIPNAME.swo  -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00E3000
+	tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00F5000
 }
 
 target create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0
@@ -104,6 +106,23 @@ if {[set $_CHIPNAME.DUAL_CORE]} {
 # Make sure that cpu0 is selected
 targets $_CHIPNAME.cpu0
 
+if { [info exists QUADSPI] && $QUADSPI } {
+   set a [llength [flash list]]
+   set _QSPINAME $_CHIPNAME.qspi
+   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000
+} else {
+   if { [info exists OCTOSPI1] && $OCTOSPI1 } {
+      set a [llength [flash list]]
+      set _OCTOSPINAME1 $_CHIPNAME.octospi1
+      flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000
+   }
+   if { [info exists OCTOSPI2] && $OCTOSPI2 } {
+      set b [llength [flash list]]
+      set _OCTOSPINAME2 $_CHIPNAME.octospi2
+      flash bank $_OCTOSPINAME2 stmqspi 0x70000000 0 0 0 $_CHIPNAME.cpu0 0x5200A000
+   }
+}
+
 # Clock after reset is HSI at 64 MHz, no need of PLL
 adapter speed 1800
 
@@ -123,7 +142,7 @@ if {[using_jtag]} {
 # usage does not work with HLA, so is not done by default. That change could be
 # made in a local configuration file if connect_assert_srst mode is needed for
 # a specific application and a non-HLA adapter is in use.
-reset_config srst_only srst_nogate
+reset_config srst_nogate
 
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
@@ -161,13 +180,20 @@ $_CHIPNAME.cpu0 configure -event examine-end {
 	stm32h7x_dbgmcu_mmw 0x03C 0x00000800 0
 	# DBGMCU_APB4FZ1 |= WDGLSD1 | WDGLSD2
 	stm32h7x_dbgmcu_mmw 0x054 0x000C0000 0
-}
 
-$_CHIPNAME.cpu0 configure -event trace-config {
-	# Set TRACECLKEN; TRACE_MODE is set to async; when using sync
-	# change this value accordingly to configure trace pins
-	# assignment
+	# Enable clock for tracing
+	# DBGMCU_CR |= TRACECLKEN
 	stm32h7x_dbgmcu_mmw 0x004 0x00100000 0
+
+	# RM0399 (id 0x450) M7+M4 with SWO Funnel
+	# RM0433 (id 0x450) M7 with SWO Funnel
+	# RM0455 (id 0x480) M7 without SWO Funnel
+	# RM0468 (id 0x483) M7 without SWO Funnel
+	# Enable CM7 and CM4 slave ports in SWO trace Funnel
+	# Works ok also on devices single core and without SWO funnel
+	# Hack, use stm32h7x_dbgmcu_mmw with big offset to control SWTF
+	# SWTF_CTRL |= ENS0 | ENS1
+	stm32h7x_dbgmcu_mmw 0x3000 0x00000003 0
 }
 
 $_CHIPNAME.cpu0 configure -event reset-init {
@@ -182,7 +208,7 @@ proc stm32h7x_get_chipname {} {
 	if {$sep == -1} {
 		return $t
 	}
-	return [string range $t 0 [expr $sep - 1]]
+	return [string range $t 0 [expr {$sep - 1}]]
 }
 
 if {[set $_CHIPNAME.DUAL_CORE]} {
@@ -206,15 +232,13 @@ if {[set $_CHIPNAME.DUAL_CORE]} {
 
 # like mrw, but with target selection
 proc stm32h7x_mrw {used_target reg} {
-	set value ""
-	$used_target mem2array value 32 $reg 1
-	return $value(0)
+	return [$used_target read_memory $reg 32 1]
 }
 
 # like mmw, but with target selection
 proc stm32h7x_mmw {used_target reg setbits clearbits} {
 	set old [stm32h7x_mrw $used_target $reg]
-	set new [expr ($old & ~$clearbits) | $setbits]
+	set new [expr {($old & ~$clearbits) | $setbits}]
 	$used_target mww $reg $new
 }
 
@@ -225,10 +249,10 @@ proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} {
 	if {![using_hla]} {
 		set _CHIPNAME [stm32h7x_get_chipname]
 		set used_target $_CHIPNAME.ap2
-		set reg_addr [expr 0xE00E1000 + $reg_offset]
+		set reg_addr [expr {0xE00E1000 + $reg_offset}]
 	} {
 		set used_target [target current]
-		set reg_addr [expr 0x5C001000 + $reg_offset]
+		set reg_addr [expr {0x5C001000 + $reg_offset}]
 	}
 
 	stm32h7x_mmw $used_target $reg_addr $setbits $clearbits