X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fstm32mp15x.cfg;h=bcdda73e90bad3ac8c5bdad8249986798899920a;hp=1b2ae7d5e71143797ba0a0bfe88c629620e6d1c7;hb=HEAD;hpb=c945d6e6160598894319860a92b602a192c2c268

diff --git a/tcl/target/stm32mp15x.cfg b/tcl/target/stm32mp15x.cfg
index 1b2ae7d5e7..bcdda73e90 100644
--- a/tcl/target/stm32mp15x.cfg
+++ b/tcl/target/stm32mp15x.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # STMicroelectronics STM32MP15x (Single/Dual Cortex-A7 plus Cortex-M4)
 # http://www.st.com/stm32mp1
 
@@ -97,6 +99,9 @@ axi_secure
 proc dbgmcu_enable_debug {} {
 	# set debug enable bits in DBGMCU_CR to get ap2 and cm4 visible
 	catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000007}
+	# freeze watchdog 1 and 2 on cores halted
+	catch {$::_CHIPNAME.ap1 mww 0xe008102c 0x00000004}
+	catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}
 }
 
 proc toggle_cpu0_dbg_claim0 {} {
@@ -106,8 +111,8 @@ proc toggle_cpu0_dbg_claim0 {} {
 }
 
 proc detect_cpu1 {} {
-	$::_CHIPNAME.ap1 mem2array cpu1_prsr 32 0xE00D2314 1
-	set dual_core [expr $cpu1_prsr(0) & 1]
+	set cpu1_prsr [$::_CHIPNAME.ap1 read_memory 0xE00D2314 32 1]
+	set dual_core [expr {$cpu1_prsr & 1}]
 	if {! $dual_core} {$::_CHIPNAME.cpu1 configure -defer-examine}
 }
 
@@ -116,7 +121,7 @@ proc rcc_enable_traceclk {} {
 }
 
 # FIXME: most of handler below will be removed once reset framework get merged
-$_CHIPNAME.ap1  configure -event reset-deassert-pre  {adapter deassert srst deassert trst;dap init;catch {$::_CHIPNAME.dap apid 1}}
+$_CHIPNAME.ap1  configure -event reset-deassert-pre  {adapter deassert srst deassert trst;catch {dap init};catch {$::_CHIPNAME.dap apid 1}}
 $_CHIPNAME.ap2  configure -event reset-deassert-pre  {dbgmcu_enable_debug;rcc_enable_traceclk}
 $_CHIPNAME.cpu0 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu0 arp_examine}
 $_CHIPNAME.cpu1 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu1 arp_examine allow-defer}