X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fstr750.cfg;h=686aede06e80e31449134e655cc9dc0d07bd5d51;hp=c467ae25b9b593258fcf1142542e7f55436d2c77;hb=42082f7c23ded282489e8ac6ec52fe94fa097cde;hpb=cc440ca1d44f0aaaf34daa365966b7b092126913 diff --git a/tcl/target/str750.cfg b/tcl/target/str750.cfg index c467ae25b9..686aede06e 100644 --- a/tcl/target/str750.cfg +++ b/tcl/target/str750.cfg @@ -19,7 +19,7 @@ if { [info exists CPUTAPID] } { } # jtag speed -jtag_khz 10 +adapter_khz 10 #use combined on interfaces or targets that can't set TRST/SRST separately reset_config trst_and_srst srst_pulls_trst @@ -29,16 +29,17 @@ reset_config trst_and_srst srst_pulls_trst jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID #jtag nTRST and nSRST delay -jtag_nsrst_delay 500 +adapter_nsrst_delay 500 jtag_ntrst_delay 500 set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 -variant arm7tdmi -$_TARGETNAME configure -event reset-start { jtag_khz 10 } +$_TARGETNAME configure -event reset-start { adapter_khz 10 } $_TARGETNAME configure -event reset-init { - jtag_khz 3000 + adapter_khz 3000 + init_smi # Because the hardware cannot be interrogated for the protection state # of sectors, initialize all the sectors to be unprotected. The initial # state is reflected by the driver, too. @@ -53,8 +54,19 @@ $_TARGETNAME configure -event gdb-flash-erase-start { $_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0 #flash bank -set _FLASHNAME $_CHIPNAME.flash +set _FLASHNAME $_CHIPNAME.flash0 flash bank $_FLASHNAME str7x 0x20000000 0x00040000 0 0 $_TARGETNAME STR75x -set _FLASHNAME $_CHIPNAME.flash +set _FLASHNAME $_CHIPNAME.flash1 flash bank $_FLASHNAME str7x 0x200C0000 0x00004000 0 0 $_TARGETNAME STR75x +# Serial NOR on SMI CS0. +set _FLASHNAME $_CHIPNAME.snor +flash bank $_FLASHNAME stmsmi 0x80000000 0 0 0 $_TARGETNAME + +source [find mem_helper.tcl] + +proc init_smi {} { + mmw 0x60000030 0x01000000 0x00000000; # enable clock for GPIO regs + mmw 0xffffe420 0x00000001 0x00000000; # set SMI_EN bit + mmw 0x90000000 0x00000001 0x00000000; # set BLOCK_EN_1 +}