X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fti_dm355.cfg;h=19fb0b6252e4b50f1f09067d8203b4658ae8aad7;hp=2551c3ed4c361d815fcd7a2b478f7da2fa935ae2;hb=HEAD;hpb=7c7467b34f11939fbce41e39dfa1b6b0e110a89c

diff --git a/tcl/target/ti_dm355.cfg b/tcl/target/ti_dm355.cfg
index 2551c3ed4c..42923733ea 100644
--- a/tcl/target/ti_dm355.cfg
+++ b/tcl/target/ti_dm355.cfg
@@ -1,10 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
-# Texas Instruments DaVinci family:  TMS320DM355
+# Texas Instruments DaVinci family: TMS320DM355
 #
 if { [info exists CHIPNAME] } {
-   set  _CHIPNAME $CHIPNAME
+   set _CHIPNAME $CHIPNAME
 } else {
-   set  _CHIPNAME dm355
+   set _CHIPNAME dm355
 }
 
 # TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
@@ -18,12 +20,12 @@ set EMU01 "-disable"
 source [find target/icepick.cfg]
 
 #
-# Also note:  when running without RTCK before the PLLs are set up, you
+# Also note: when running without RTCK before the PLLs are set up, you
 # may need to slow the JTAG clock down quite a lot (under 2 MHz).
 #
 
 # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
-if { [info exists ETB_TAPID ] } {
+if { [info exists ETB_TAPID] } {
    set _ETB_TAPID $ETB_TAPID
 } else {
    set _ETB_TAPID 0x2b900f0f
@@ -33,7 +35,7 @@ jtag configure $_CHIPNAME.etb -event tap-enable \
 	"icepick_c_tapenable $_CHIPNAME.jrc 1"
 
 # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
-if { [info exists CPU_TAPID ] } {
+if { [info exists CPU_TAPID] } {
    set _CPU_TAPID $CPU_TAPID
 } else {
    set _CPU_TAPID 0x07926001
@@ -43,7 +45,7 @@ jtag configure $_CHIPNAME.arm -event tap-enable \
 	"icepick_c_tapenable $_CHIPNAME.jrc 0"
 
 # Primary TAP: ICEpick (JTAG route controller) and boundary scan
-if { [info exists JRC_TAPID ] } {
+if { [info exists JRC_TAPID] } {
    set _JRC_TAPID $JRC_TAPID
 } else {
    set _JRC_TAPID 0x0b73b02f
@@ -81,7 +83,7 @@ dict set dm355 uart2		0x01e06000
 source [find target/davinci.cfg]
 
 ################
-# GDB target:  the ARM, using SRAM1 for scratch.  SRAM0 (also 16K)
+# GDB target: the ARM, using SRAM1 for scratch.  SRAM0 (also 16K)
 # and the ETB memory (4K) are other options, while trace is unused.
 set _TARGETNAME $_CHIPNAME.arm
 
@@ -90,7 +92,7 @@ target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
 # NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
 # and that the work area is used only with a kernel mmu context ...
 $_TARGETNAME configure \
-	-work-area-virt [expr 0xfffe0000 + 0x4000] \
+	-work-area-virt [expr {0xfffe0000 + 0x4000}] \
 	-work-area-phys [dict get $dm355 sram1] \
 	-work-area-size 0x4000 \
 	-work-area-backup 0
@@ -98,8 +100,8 @@ $_TARGETNAME configure \
 # be absolutely certain the JTAG clock will work with the worst-case
 # CLKIN = 24 MHz (best case: 36 MHz) even when no bootloader turns
 # on the PLL and starts using it.  OK to speed up after clock setup.
-jtag_rclk 1500
-$_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
 
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable