X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fti_k3.cfg;fp=tcl%2Ftarget%2Fti_k3.cfg;h=e05b81a17c56bc709882845a16214d37879a7d5a;hp=78ee8b2ca72f1624099fc5f8571c583e2648db35;hb=4b879bb01737f11a11f05c3b4feb09e6ddc85a5d;hpb=00b07390826f7cd5f72bc036e3907a87c6cbc33d

diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 78ee8b2ca7..e05b81a17c 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -56,6 +56,7 @@ set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}
 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
 set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
 set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
+set _r5_ap_num 1
 
 # Finally an General Purpose(GP) MCU
 set CM4_CTIBASE		{0x20001000}
@@ -359,12 +360,12 @@ if { $_v8_smp_debug == 0 } {
 
 for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
 	set _r5_name [lindex $R5_NAMES $_core]
-	cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num 1 \
+	cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num $_r5_ap_num \
 		-baseaddr [lindex $R5_CTIBASE $_core]
 
 	# inactive core examination will fail - wait till startup of additional core
 	target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
-		-dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine \
+		-dbgbase [lindex $R5_DBGBASE $_core] -ap-num $_r5_ap_num -defer-examine \
 		-rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_r5_name]
 
 	$_TARGETNAME.$_r5_name configure -event gdb-attach {