target/arm_adi_v5: fix sync CSW cache on apreg write 79/4679/3
authorAntonio Borneo <>
Fri, 21 Sep 2018 13:52:02 +0000 (15:52 +0200)
committerMatthias Welwarsky <>
Sat, 27 Oct 2018 13:37:05 +0000 (14:37 +0100)
target/arm_adi_v5: fix sync CSW cache on apreg write

Commit 0057c71ab6b81d0679b232318fc5f84b4becc471 updates the OpenOCD
cached values of CSW and TAR registers if these registers are modified
by an apreg command.
The condition to force the update of CSW cache is incorrect and it will
erase the default CSW value.
Moreover, calling mem_ap_setup_csw() does not honor the value requested
in the apreg command because such value is incorrectly bitwise or-ed
with csw_default.

Fix it by updating csw_value, instead of erasing csw_default, and writing
directly in CSW register the new value from the command line.

Change-Id: I40273cb64d22ccfb9b6d3499bd39b586eb60de38
Fixes: 0057c71ab6b8 ("target/arm_adi_v5: sync CSW and TAR cache on apreg write")
Signed-off-by: Antonio Borneo <>
Tested-by: jenkins
Reviewed-by: Christopher Head <>
Reviewed-by: Tomas Vanek <>

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