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target/zynqmp : Add AXI AP access port 63/6263/3
authorOlivier DANET <odanet@caramail.com>
Mon, 17 May 2021 12:47:14 +0000 (14:47 +0200)
committerAntonio Borneo <borneo.antonio@gmail.com>
Sat, 22 May 2021 09:12:01 +0000 (10:12 +0100)
commit4e872a797f81595d5de790138bdec62f2bf175f0
tree82d5e8b2e822bb8cd9b145e823fb0328528c7cc4tree | snapshot
parent036de3b48217e9c0b5ec0bbf6638e9cad6cae517commit | diff
target/zynqmp : Add AXI AP access port

The Xilinx Zynq UltraScale+ SoC have an "AXI-AP" access port for direct memory accesses without halting CPUs.

Change-Id: I6303331c217795657575de4759444938e775dee1
Signed-off-by: Olivier DANET <odanet@caramail.com>
Reviewed-on: http://openocd.zylin.com/6263
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
tcl/target/xilinx_zynqmp.cfg diff | blob | history
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