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flash/stm32l4x: add support of STM32WL5x dual core 50/6050/16
authorTarek BOCHKATI <tarek.bouchkati@gmail.com>
Thu, 4 Feb 2021 21:43:52 +0000 (22:43 +0100)
committerOleksij Rempel <linux@rempel-privat.de>
Thu, 26 Aug 2021 13:13:02 +0000 (13:13 +0000)
commit6c1e1a212a8c044ae778c526851fe909bf219e90
treee59a207ce19388a5805e6ed05a392a6c56c96722tree | snapshot
parent64fbd607874bbe9726cf1d09c2cbf547bd9d804ccommit | diff
flash/stm32l4x: add support of STM32WL5x dual core

according the RM0453, the second core  have a different Flash CR and SR
registers for flash operations (called C2CR and C2SR).
so we need to a different flash_regs than older L4 devices.
@see stm32wl_cpu2_flash_regs

the C2CR register don't contain LOCK and OPTLOCK bits, and this explain
the addition of new register index called STM32_FLASH_CR_WLK_INDEX to
look-up the CR with lock, to be used in locking/unlocking the flash.

note: DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1,
to solve this read the UID64 (IEEE 64-bit unique device ID register)

Change-Id: Ifb6e291bf97f814f0b9987b2c40f3037959f7af4
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6050
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
src/flash/nor/stm32l4x.c diff | blob | history
src/flash/nor/stm32l4x.h diff | blob | history
tcl/target/stm32wlx.cfg diff | blob | history
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