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(parent: 4d1b293) | patch
target/riscv: fix 'reset run' after 'reset halt' 61/6961/2
authorTomas Vanek <vanekt@fbl.cz>
Sun, 1 May 2022 13:20:24 +0000 (15:20 +0200)
committerTomas Vanek <vanekt@fbl.cz>
Wed, 18 May 2022 09:03:41 +0000 (09:03 +0000)
commit7d2ea186cf212c64a8e5b10725e0a2512a137fbe
treeb8cad6ee1059d448729bf1c0aa47bd7d8551f35btree | snapshot
parent4d1b29313ace5b26687f75fb132c04f91cc1edcbcommit | diff
target/riscv: fix 'reset run' after 'reset halt'

'reset halt' does not clear DM_DMCONTROL_HALTREQ at deassert_reset().
If hw reset line is configured e.g. 'reset_config srst_only'
the folowing 'reset run' halts:

 > gd32v.cpu curstate
 running

 > reset halt
 JTAG tap: gd32v.cpu tap/device found: 0x1000563d (mfg: 0x31e ...
 > gd32v.cpu curstate
 halted

 > reset
 JTAG tap: gd32v.cpu tap/device found: 0x1000563d (mfg: 0x31e ...
 > gd32v.cpu curstate
 halted <<<<---- wrong!!!

 > reset
 JTAG tap: gd32v.cpu tap/device found: 0x1000563d (mfg: 0x31e ...
 > gd32v.cpu curstate
 running

Clear DM_DMCONTROL_HALTREQ when acking reset.

Change-Id: Iae0454b425e81e64774b9785bb5ba1d4564d940b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6961
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
src/target/riscv/riscv-013.c diff | blob | history
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