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target/cortex_m: allow setting the type of a breakpoint 29/4429/9
authorTomas Vanek <vanekt@fbl.cz>
Thu, 22 Feb 2018 23:12:50 +0000 (00:12 +0100)
committerMatthias Welwarsky <matthias@welwarsky.de>
Thu, 12 Apr 2018 19:49:18 +0000 (20:49 +0100)
commit81d0b769a65bf15dda2fd51cd4aee50bb0dc16fb
tree5c3639a420ed9616c6d3717e079ace730851be51tree | snapshot
parent09076d10dd553dc63f08e74aedb1b6aa030857f9commit | diff
target/cortex_m: allow setting the type of a breakpoint

Cortex-M target used 'auto_bp_type' mode. The requested type
of breakpoint was ignored and hard (FPB) breakpoints were set in
'code memory area' 0x00000000-0x1fffffff, soft breakpoints were set above
0x20000000.

The code memory area of Cortex-M does not mean the memory is flash and
vice versa. External flash (parallel or QSPI) is usually mapped above
code memory area. Cortex-M7 ITCM RAM is mapped at 0. Kinetis
has a RAM block under 0x20000000 boundary.

Remove 'auto_bp_type' mode, set breakpoints to requested type.

Change 'cortex_m maskisr auto' handling to use a hard temporary
breakpoint everywhere: it can also workaround not working soft breakpoints
on Cortex-M7 with ICache enabled.

Change-Id: I7a9f9464c5e10bfd7f17cba1037ed07a064fa2e8
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4429
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
doc/openocd.texi diff | blob | history
src/target/cortex_m.c diff | blob | history
src/target/cortex_m.h diff | blob | history
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