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(parent: 45b4998) | patch
Correct ZynqMP configuration to be appropriately named 50/4850/2
authorJonathan McDowell <noodles@earth.li>
Mon, 14 Jan 2019 10:51:37 +0000 (10:51 +0000)
committerMatthias Welwarsky <matthias@welwarsky.de>
Wed, 23 Jan 2019 15:26:48 +0000 (15:26 +0000)
commitd2fb461621dc97a611e7bb44a2a64e1efe300875
treeb2ebaabe29efe6ab9d95bbac81e580a25d6f4eedtree | snapshot
parent45b4998e9369029d48c1f33fbccb1a525793cd46commit | diff
Correct ZynqMP configuration to be appropriately named

The xilinx_ultrascale.cfg target is actually the configuration for a
ZynqMP, which is a combination of an UltraScale+ FPGA core and a quad
core A53. Update the filename/comments to reflect this, and include
the tap IDs for all known FPGA cores for this part.

Change-Id: I70dfcc99861a482b83b6a795e83021d9cf1fe047
Signed-off-by: Jonathan McDowell <noodles@earth.li>
Reviewed-on: http://openocd.zylin.com/4850
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
tcl/board/avnet_ultrazed-eg.cfg diff | blob | history
tcl/target/xilinx_zynqmp.cfg [moved from tcl/target/xilinx_ultrascale.cfg with 75% similarity] diff | blob | history
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