Remove misleading typedef and redundant suffix from struct arm_jtag.
23 files changed:
+ struct arm_jtag *jtag_info;
unsigned int buflen;
unsigned int bufalign;
};
unsigned int buflen;
unsigned int bufalign;
};
struct str9xpec_flash_controller *str9xpec_info;
armv4_5_common_t *armv4_5 = NULL;
struct arm7_9_common *arm7_9 = NULL;
struct str9xpec_flash_controller *str9xpec_info;
armv4_5_common_t *armv4_5 = NULL;
struct arm7_9_common *arm7_9 = NULL;
- arm_jtag_t *jtag_info = NULL;
+ struct arm_jtag *jtag_info = NULL;
{
int retval;
struct arm720t_common *arm720t = target_to_arm720(target);
{
int retval;
struct arm720t_common *arm720t = target_to_arm720(target);
+ struct arm_jtag *jtag_info;
struct scan_field fields[2];
uint8_t out_buf[4];
uint8_t instruction_buf = instruction;
struct scan_field fields[2];
uint8_t out_buf[4];
uint8_t instruction_buf = instruction;
int retval;
target_t *target = get_current_target(cmd_ctx);
struct arm720t_common *arm720t = target_to_arm720(target);
int retval;
target_t *target = get_current_target(cmd_ctx);
struct arm720t_common *arm720t = target_to_arm720(target);
+ struct arm_jtag *jtag_info;
retval = arm720t_verify_pointer(cmd_ctx, arm720t);
if (retval != ERROR_OK)
retval = arm720t_verify_pointer(cmd_ctx, arm720t);
if (retval != ERROR_OK)
{
int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
{
int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* set RESTART instruction */
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* set RESTART instruction */
static uint8_t check_value[4], check_mask[4];
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
static uint8_t check_value[4], check_mask[4];
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* set RESTART instruction */
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* set RESTART instruction */
int arm7_9_target_request_data(target_t *target, uint32_t size, uint8_t *buffer)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int arm7_9_target_request_data(target_t *target, uint32_t size, uint8_t *buffer)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
uint32_t *data;
int retval = ERROR_OK;
uint32_t i;
uint32_t *data;
int retval = ERROR_OK;
uint32_t i;
if (!target_was_examined(target))
return ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
if (!target_was_examined(target))
return ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
if (!target->dbg_msg_enabled)
reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
if (!target->dbg_msg_enabled)
int arm7_9_restart_core(struct target_s *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int arm7_9_restart_core(struct target_s *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* set RESTART instruction */
jtag_set_end_state(TAP_IDLE);
/* set RESTART instruction */
jtag_set_end_state(TAP_IDLE);
struct arm armv4_5_common;
uint32_t common_magic;
struct arm armv4_5_common;
uint32_t common_magic;
- arm_jtag_t jtag_info; /**< JTAG information for target */
+ struct arm_jtag jtag_info; /**< JTAG information for target */
reg_cache_t *eice_cache; /**< Embedded ICE register cache */
uint32_t arm_bkpt; /**< ARM breakpoint instruction */
reg_cache_t *eice_cache; /**< Embedded ICE register cache */
uint32_t arm_bkpt; /**< ARM breakpoint instruction */
static const int arm7tdmi_num_bits[] = {1, 32};
static const int arm7tdmi_num_bits[] = {1, 32};
-static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, uint32_t out, int breakpoint)
+static __inline int arm7tdmi_clock_out_inner(struct arm_jtag *jtag_info, uint32_t out, int breakpoint)
{
uint32_t values[2]={breakpoint, flip_u32(out, 32)};
{
uint32_t values[2]={breakpoint, flip_u32(out, 32)};
*
* FIXME remove the unused "deprecated" parameter
*/
*
* FIXME remove the unused "deprecated" parameter
*/
-static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info,
+static __inline int arm7tdmi_clock_out(struct arm_jtag *jtag_info,
uint32_t out, uint32_t *deprecated, int breakpoint)
{
jtag_set_end_state(TAP_DRPAUSE);
uint32_t out, uint32_t *deprecated, int breakpoint)
{
jtag_set_end_state(TAP_DRPAUSE);
}
/* clock the target, reading the databus */
}
/* clock the target, reading the databus */
-static int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, uint32_t *in)
+static int arm7tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in)
{
int retval = ERROR_OK;
struct scan_field fields[2];
{
int retval = ERROR_OK;
struct scan_field fields[2];
* the *in pointer points to a buffer where elements of 'size' bytes
* are stored in big (be == 1) or little (be == 0) endianness
*/
* the *in pointer points to a buffer where elements of 'size' bytes
* are stored in big (be == 1) or little (be == 0) endianness
*/
-static int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info,
+static int arm7tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info,
void *in, int size, int be)
{
int retval = ERROR_OK;
void *in, int size, int be)
{
int retval = ERROR_OK;
uint32_t *r0, uint32_t *pc)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
uint32_t *r0, uint32_t *pc)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* save r0 before using it and put system in ARM state
* to allow common handling of ARM and THUMB debugging */
/* save r0 before using it and put system in ARM state
* to allow common handling of ARM and THUMB debugging */
{
int i;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
{
int i;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* STMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
/* STMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
{
int i;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
{
int i;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
uint32_t *buf_u32 = buffer;
uint16_t *buf_u16 = buffer;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
uint32_t *buf_u32 = buffer;
uint16_t *buf_u16 = buffer;
static void arm7tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
static void arm7tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* MRS r0, cpsr */
arm7tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), NULL, 0);
/* MRS r0, cpsr */
arm7tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), NULL, 0);
static void arm7tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
static void arm7tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
uint8_t xpsr_im, int rot, int spsr)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
uint8_t xpsr_im, int rot, int spsr)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
{
int i;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
{
int i;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
/* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
static void arm7tdmi_load_word_regs(target_t *target, uint32_t mask)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
static void arm7tdmi_load_word_regs(target_t *target, uint32_t mask)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* put system-speed load-multiple into the pipeline */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
/* put system-speed load-multiple into the pipeline */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
static void arm7tdmi_load_hword_reg(target_t *target, int num)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
static void arm7tdmi_load_hword_reg(target_t *target, int num)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* put system-speed load half-word into the pipeline */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
/* put system-speed load half-word into the pipeline */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
static void arm7tdmi_load_byte_reg(target_t *target, int num)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
static void arm7tdmi_load_byte_reg(target_t *target, int num)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* put system-speed load byte into the pipeline */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
/* put system-speed load byte into the pipeline */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
static void arm7tdmi_store_word_regs(target_t *target, uint32_t mask)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
static void arm7tdmi_store_word_regs(target_t *target, uint32_t mask)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* put system-speed store-multiple into the pipeline */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
/* put system-speed store-multiple into the pipeline */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
static void arm7tdmi_store_hword_reg(target_t *target, int num)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
static void arm7tdmi_store_hword_reg(target_t *target, int num)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* put system-speed store half-word into the pipeline */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
/* put system-speed store half-word into the pipeline */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
static void arm7tdmi_store_byte_reg(target_t *target, int num)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
static void arm7tdmi_store_byte_reg(target_t *target, int num)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* put system-speed store byte into the pipeline */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
/* put system-speed store byte into the pipeline */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
static void arm7tdmi_write_pc(target_t *target, uint32_t pc)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
static void arm7tdmi_write_pc(target_t *target, uint32_t pc)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
/* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
static void arm7tdmi_branch_resume(target_t *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
static void arm7tdmi_branch_resume(target_t *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_B(0xfffffa, 0), 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_B(0xfffffa, 0), 0);
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
LOG_DEBUG("-");
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
LOG_DEBUG("-");
if (arm7_9->armv4_5_common.etm)
{
if (arm7_9->armv4_5_common.etm)
{
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
(*cache_p)->next = etm_build_reg_cache(target,
jtag_info, arm7_9->armv4_5_common.etm);
arm7_9->armv4_5_common.etm->reg_cache = (*cache_p)->next;
(*cache_p)->next = etm_build_reg_cache(target,
jtag_info, arm7_9->armv4_5_common.etm);
arm7_9->armv4_5_common.etm->reg_cache = (*cache_p)->next;
int reg_addr, uint32_t *value)
{
struct arm920t_common *arm920t = target_to_arm920(target);
int reg_addr, uint32_t *value)
{
struct arm920t_common *arm920t = target_to_arm920(target);
+ struct arm_jtag *jtag_info;
struct scan_field fields[4];
uint8_t access_type_buf = 1;
uint8_t reg_addr_buf = reg_addr & 0x3f;
struct scan_field fields[4];
uint8_t access_type_buf = 1;
uint8_t reg_addr_buf = reg_addr & 0x3f;
int reg_addr, uint32_t value)
{
struct arm920t_common *arm920t = target_to_arm920(target);
int reg_addr, uint32_t value)
{
struct arm920t_common *arm920t = target_to_arm920(target);
+ struct arm_jtag *jtag_info;
struct scan_field fields[4];
uint8_t access_type_buf = 1;
uint8_t reg_addr_buf = reg_addr & 0x3f;
struct scan_field fields[4];
uint8_t access_type_buf = 1;
uint8_t reg_addr_buf = reg_addr & 0x3f;
{
int retval;
struct arm920t_common *arm920t = target_to_arm920(target);
{
int retval;
struct arm920t_common *arm920t = target_to_arm920(target);
+ struct arm_jtag *jtag_info;
struct scan_field fields[4];
uint8_t access_type_buf = 0; /* interpreted access */
uint8_t reg_addr_buf = 0x0;
struct scan_field fields[4];
uint8_t access_type_buf = 0; /* interpreted access */
uint8_t reg_addr_buf = 0x0;
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
struct scan_field fields[4];
uint8_t address_buf[2];
uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
struct scan_field fields[4];
uint8_t address_buf[2];
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
struct scan_field fields[4];
uint8_t value_buf[4];
uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
struct scan_field fields[4];
uint8_t value_buf[4];
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
struct scan_field fields[3];
uint8_t reg_addr_buf = reg_addr & 0x3f;
uint8_t nr_w_buf = 0;
struct scan_field fields[3];
uint8_t reg_addr_buf = reg_addr & 0x3f;
uint8_t nr_w_buf = 0;
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
struct scan_field fields[3];
uint8_t reg_addr_buf = reg_addr & 0x3f;
uint8_t nr_w_buf = 1;
struct scan_field fields[3];
uint8_t reg_addr_buf = reg_addr & 0x3f;
uint8_t nr_w_buf = 1;
/* put an instruction in the ARM9TDMI pipeline or write the data bus,
* and optionally read data
*/
/* put an instruction in the ARM9TDMI pipeline or write the data bus,
* and optionally read data
*/
-int arm9tdmi_clock_out(arm_jtag_t *jtag_info, uint32_t instr,
+int arm9tdmi_clock_out(struct arm_jtag *jtag_info, uint32_t instr,
uint32_t out, uint32_t *in, int sysspeed)
{
int retval = ERROR_OK;
uint32_t out, uint32_t *in, int sysspeed)
{
int retval = ERROR_OK;
}
/* just read data (instruction and data-out = don't care) */
}
/* just read data (instruction and data-out = don't care) */
-int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, uint32_t *in)
+int arm9tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in)
{
int retval = ERROR_OK;;
struct scan_field fields[3];
{
int retval = ERROR_OK;;
struct scan_field fields[3];
* the *in pointer points to a buffer where elements of 'size' bytes
* are stored in big (be == 1) or little (be == 0) endianness
*/
* the *in pointer points to a buffer where elements of 'size' bytes
* are stored in big (be == 1) or little (be == 0) endianness
*/
-int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info,
+int arm9tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info,
void *in, int size, int be)
{
int retval = ERROR_OK;
void *in, int size, int be)
{
int retval = ERROR_OK;
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* save r0 before using it and put system in ARM state
* to allow common handling of ARM and THUMB debugging */
/* save r0 before using it and put system in ARM state
* to allow common handling of ARM and THUMB debugging */
{
int i;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
{
int i;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* STMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
/* STMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
{
int i;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
{
int i;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
uint32_t *buf_u32 = buffer;
uint16_t *buf_u16 = buffer;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
uint32_t *buf_u32 = buffer;
uint16_t *buf_u16 = buffer;
static void arm9tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
static void arm9tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* MRS r0, cpsr */
arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
/* MRS r0, cpsr */
arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
static void arm9tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
static void arm9tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
uint8_t xpsr_im, int rot, int spsr)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
uint8_t xpsr_im, int rot, int spsr)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
{
int i;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
{
int i;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
/* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
void arm9tdmi_load_word_regs(target_t *target, uint32_t mask)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
void arm9tdmi_load_word_regs(target_t *target, uint32_t mask)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* put system-speed load-multiple into the pipeline */
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
/* put system-speed load-multiple into the pipeline */
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
void arm9tdmi_load_hword_reg(target_t *target, int num)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
void arm9tdmi_load_hword_reg(target_t *target, int num)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* put system-speed load half-word into the pipeline */
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
/* put system-speed load half-word into the pipeline */
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
void arm9tdmi_load_byte_reg(target_t *target, int num)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
void arm9tdmi_load_byte_reg(target_t *target, int num)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* put system-speed load byte into the pipeline */
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
/* put system-speed load byte into the pipeline */
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
void arm9tdmi_store_word_regs(target_t *target, uint32_t mask)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
void arm9tdmi_store_word_regs(target_t *target, uint32_t mask)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* put system-speed store-multiple into the pipeline */
arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
/* put system-speed store-multiple into the pipeline */
arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
void arm9tdmi_store_hword_reg(target_t *target, int num)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
void arm9tdmi_store_hword_reg(target_t *target, int num)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* put system-speed store half-word into the pipeline */
arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
/* put system-speed store half-word into the pipeline */
arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
void arm9tdmi_store_byte_reg(target_t *target, int num)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
void arm9tdmi_store_byte_reg(target_t *target, int num)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* put system-speed store byte into the pipeline */
arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
/* put system-speed store byte into the pipeline */
arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
static void arm9tdmi_write_pc(target_t *target, uint32_t pc)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
static void arm9tdmi_write_pc(target_t *target, uint32_t pc)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
/* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
void arm9tdmi_branch_resume(target_t *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
void arm9tdmi_branch_resume(target_t *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* LDMIA r0-15, [r0] at debug speed
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* LDMIA r0-15, [r0] at debug speed
if (arm7_9->armv4_5_common.etm)
{
if (arm7_9->armv4_5_common.etm)
{
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
(*cache_p)->next = etm_build_reg_cache(target,
jtag_info, arm7_9->armv4_5_common.etm);
arm7_9->armv4_5_common.etm->reg_cache = (*cache_p)->next;
(*cache_p)->next = etm_build_reg_cache(target,
jtag_info, arm7_9->armv4_5_common.etm);
arm7_9->armv4_5_common.etm->reg_cache = (*cache_p)->next;
struct arm9tdmi_common *arm9tdmi, struct jtag_tap *tap);
int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);
struct arm9tdmi_common *arm9tdmi, struct jtag_tap *tap);
int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);
-int arm9tdmi_clock_out(arm_jtag_t *jtag_info,
+int arm9tdmi_clock_out(struct arm_jtag *jtag_info,
uint32_t instr, uint32_t out, uint32_t *in, int sysspeed);
uint32_t instr, uint32_t out, uint32_t *in, int sysspeed);
-int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, uint32_t *in);
-int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info,
+int arm9tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in);
+int arm9tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info,
void *in, int size, int be);
void arm9tdmi_read_core_regs(target_t *target,
uint32_t mask, uint32_t* core_regs[16]);
void *in, int size, int be);
void arm9tdmi_read_core_regs(target_t *target,
uint32_t mask, uint32_t* core_regs[16]);
/* Scan out and in from target ordered uint8_t buffers */
int adi_jtag_dp_scan(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
{
/* Scan out and in from target ordered uint8_t buffers */
int adi_jtag_dp_scan(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
{
- arm_jtag_t *jtag_info = swjdp->jtag_info;
+ struct arm_jtag *jtag_info = swjdp->jtag_info;
struct scan_field fields[2];
uint8_t out_addr_buf;
struct scan_field fields[2];
uint8_t out_addr_buf;
/* Scan out and in from host ordered uint32_t variables */
int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
{
/* Scan out and in from host ordered uint32_t variables */
int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
{
- arm_jtag_t *jtag_info = swjdp->jtag_info;
+ struct arm_jtag *jtag_info = swjdp->jtag_info;
struct scan_field fields[2];
uint8_t out_value_buf[4];
uint8_t out_addr_buf;
struct scan_field fields[2];
uint8_t out_value_buf[4];
uint8_t out_addr_buf;
struct swjdp_reg
{
int addr;
struct swjdp_reg
{
int addr;
+ struct arm_jtag *jtag_info;
+ struct arm_jtag *jtag_info;
/* Control config */
uint32_t dp_ctrl_stat;
/* Support for several AP's in one DAP */
/* Control config */
uint32_t dp_ctrl_stat;
/* Support for several AP's in one DAP */
#define _ARM_JTAG_SCAN_N_CHECK_
#endif
#define _ARM_JTAG_SCAN_N_CHECK_
#endif
-int arm_jtag_set_instr(arm_jtag_t *jtag_info, uint32_t new_instr, void *no_verify_capture)
+int arm_jtag_set_instr(struct arm_jtag *jtag_info, uint32_t new_instr, void *no_verify_capture)
{
struct jtag_tap *tap;
tap = jtag_info->tap;
{
struct jtag_tap *tap;
tap = jtag_info->tap;
-int arm_jtag_scann(arm_jtag_t *jtag_info, uint32_t new_scan_chain)
+int arm_jtag_scann(struct arm_jtag *jtag_info, uint32_t new_scan_chain)
{
int retval = ERROR_OK;
if (jtag_info->cur_scan_chain != new_scan_chain)
{
int retval = ERROR_OK;
if (jtag_info->cur_scan_chain != new_scan_chain)
int arm_jtag_reset_callback(enum jtag_event event, void *priv)
{
int arm_jtag_reset_callback(enum jtag_event event, void *priv)
{
- arm_jtag_t *jtag_info = priv;
+ struct arm_jtag *jtag_info = priv;
if (event == JTAG_TRST_ASSERTED)
{
if (event == JTAG_TRST_ASSERTED)
{
-int arm_jtag_setup_connection(arm_jtag_t *jtag_info)
+int arm_jtag_setup_connection(struct arm_jtag *jtag_info)
{
jtag_info->scann_instr = 0x2;
jtag_info->cur_scan_chain = 0;
{
jtag_info->scann_instr = 0x2;
jtag_info->cur_scan_chain = 0;
-typedef struct arm_jtag_s
uint32_t cur_scan_chain;
uint32_t intest_instr;
uint32_t cur_scan_chain;
uint32_t intest_instr;
-int arm_jtag_set_instr(arm_jtag_t *jtag_info,
+int arm_jtag_set_instr(struct arm_jtag *jtag_info,
uint32_t new_instr, void *verify_capture);
uint32_t new_instr, void *verify_capture);
-int arm_jtag_scann(arm_jtag_t *jtag_info, uint32_t new_scan_chain);
-int arm_jtag_setup_connection(arm_jtag_t *jtag_info);
+int arm_jtag_scann(struct arm_jtag *jtag_info, uint32_t new_scan_chain);
+int arm_jtag_setup_connection(struct arm_jtag *jtag_info);
/* JTAG buffers to host, be and le buffers, flipping variants */
int arm_jtag_buf_to_u32_flip(uint8_t *in_buf, void *priv, struct scan_field_s *field);
/* JTAG buffers to host, be and le buffers, flipping variants */
int arm_jtag_buf_to_u32_flip(uint8_t *in_buf, void *priv, struct scan_field_s *field);
typedef struct cortex_a8_common_s
{
int common_magic;
typedef struct cortex_a8_common_s
{
int common_magic;
+ struct arm_jtag jtag_info;
/* Context information */
uint32_t cpudbg_dscr;
/* Context information */
uint32_t cpudbg_dscr;
typedef struct cortex_m3_common_s
{
int common_magic;
typedef struct cortex_m3_common_s
{
int common_magic;
+ struct arm_jtag jtag_info;
/* Context information */
uint32_t dcb_dhcsr;
/* Context information */
uint32_t dcb_dhcsr;
reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
reg_t *reg_list = NULL;
embeddedice_reg_t *arch_info = NULL;
reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
reg_t *reg_list = NULL;
embeddedice_reg_t *arch_info = NULL;
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
int num_regs = ARRAY_SIZE(eice_regs);
int i;
int eice_version = 0;
int num_regs = ARRAY_SIZE(eice_regs);
int i;
int eice_version = 0;
* functional clock, so the 50+ JTAG clocks needed to receive the word
* allow hundreds of instruction cycles (per word) in the target.
*/
* functional clock, so the 50+ JTAG clocks needed to receive the word
* allow hundreds of instruction cycles (per word) in the target.
*/
-int embeddedice_receive(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size)
+int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
{
struct scan_field fields[3];
uint8_t field1_out[1];
{
struct scan_field fields[3];
uint8_t field1_out[1];
* functional clock, so the 50+ JTAG clocks needed to receive the word
* allow hundreds of instruction cycles (per word) in the target.
*/
* functional clock, so the 50+ JTAG clocks needed to receive the word
* allow hundreds of instruction cycles (per word) in the target.
*/
-int embeddedice_send(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size)
+int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
{
struct scan_field fields[3];
uint8_t field0_out[4];
{
struct scan_field fields[3];
uint8_t field0_out[4];
/**
* Poll DCC control register until read or write handshake completes.
*/
/**
* Poll DCC control register until read or write handshake completes.
*/
-int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, uint32_t timeout)
+int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeout)
{
struct scan_field fields[3];
uint8_t field0_in[4];
{
struct scan_field fields[3];
uint8_t field0_in[4];
typedef struct embeddedice_reg_s
{
int addr;
typedef struct embeddedice_reg_s
{
int addr;
+ struct arm_jtag *jtag_info;
} embeddedice_reg_t;
reg_cache_t* embeddedice_build_reg_cache(target_t *target,
} embeddedice_reg_t;
reg_cache_t* embeddedice_build_reg_cache(target_t *target,
void embeddedice_set_reg(reg_t *reg, uint32_t value);
int embeddedice_set_reg_w_exec(reg_t *reg, uint8_t *buf);
void embeddedice_set_reg(reg_t *reg, uint32_t value);
int embeddedice_set_reg_w_exec(reg_t *reg, uint8_t *buf);
-int embeddedice_receive(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size);
-int embeddedice_send(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size);
+int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size);
+int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size);
-int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, uint32_t timeout);
+int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeout);
/* If many embeddedice_write_reg() follow eachother, then the >1 invocations can be this faster version of
* embeddedice_write_reg
/* If many embeddedice_write_reg() follow eachother, then the >1 invocations can be this faster version of
* embeddedice_write_reg
-static void etm_reg_add(unsigned bcd_vers, arm_jtag_t *jtag_info,
+static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
reg_cache_t *cache, etm_reg_t *ereg,
const struct etm_reg_info *r, unsigned nreg)
{
reg_cache_t *cache, etm_reg_t *ereg,
const struct etm_reg_info *r, unsigned nreg)
{
}
reg_cache_t *etm_build_reg_cache(target_t *target,
}
reg_cache_t *etm_build_reg_cache(target_t *target,
- arm_jtag_t *jtag_info, etm_context_t *etm_ctx)
+ struct arm_jtag *jtag_info, etm_context_t *etm_ctx)
{
reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
reg_t *reg_list = NULL;
{
reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
reg_t *reg_list = NULL;
{
uint32_t value;
const struct etm_reg_info *reg_info;
{
uint32_t value;
const struct etm_reg_info *reg_info;
+ struct arm_jtag *jtag_info;
} etm_reg_t;
typedef enum
} etm_reg_t;
typedef enum
} etmv1_branch_reason_t;
reg_cache_t* etm_build_reg_cache(target_t *target,
} etmv1_branch_reason_t;
reg_cache_t* etm_build_reg_cache(target_t *target,
- arm_jtag_t *jtag_info, etm_context_t *etm_ctx);
+ struct arm_jtag *jtag_info, etm_context_t *etm_ctx);
int etm_setup(target_t *target);
int etm_setup(target_t *target);
{
int i;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
{
int i;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* STMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
/* STMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
{
int i;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
{
int i;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
uint32_t *buf_u32 = buffer;
uint16_t *buf_u16 = buffer;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
uint32_t *buf_u32 = buffer;
uint16_t *buf_u16 = buffer;
static void fa526_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
static void fa526_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* MRS r0, cpsr */
arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
/* MRS r0, cpsr */
arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
static void fa526_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
static void fa526_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
uint8_t xpsr_im, int rot, int spsr)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
uint8_t xpsr_im, int rot, int spsr)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
{
int i;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
{
int i;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
/* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
static void fa526_write_pc(target_t *target, uint32_t pc)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
static void fa526_write_pc(target_t *target, uint32_t pc)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
/* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
return arm7_9_assert_reset(target);
}
return arm7_9_assert_reset(target);
}
-int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, uint32_t instr)
+int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr)
{
struct scan_field fields[3];
uint8_t out_buf[4];
{
struct scan_field fields[3];
uint8_t out_buf[4];
{
armv4_5_common_t *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
{
armv4_5_common_t *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/*
* save r0 before using it and put system in ARM state
/*
* save r0 before using it and put system in ARM state
int i;
armv4_5_common_t *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
int i;
armv4_5_common_t *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
int i;
armv4_5_common_t *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
int i;
armv4_5_common_t *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
uint32_t *buf_u32 = buffer;
uint16_t *buf_u16 = buffer;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
uint32_t *buf_u32 = buffer;
uint16_t *buf_u16 = buffer;
{
armv4_5_common_t *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
{
armv4_5_common_t *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
{
armv4_5_common_t *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
{
armv4_5_common_t *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
{
armv4_5_common_t *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
{
armv4_5_common_t *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
int i;
armv4_5_common_t *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
int i;
armv4_5_common_t *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
{
armv4_5_common_t *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
{
armv4_5_common_t *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
armv4_5_common_t *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
armv4_5_common_t *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
uint32_t pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
uint32_t pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
{
armv4_5_common_t *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
{
armv4_5_common_t *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
int err;
arm9tdmi_clock_out(jtag_info, ARMV4_5_MRC(15, op1, 0, CRn, CRm, op2), 0, NULL, 0);
int err;
arm9tdmi_clock_out(jtag_info, ARMV4_5_MRC(15, op1, 0, CRn, CRm, op2), 0, NULL, 0);
{
armv4_5_common_t *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
{
armv4_5_common_t *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 1, 0, 0), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 1, 0, 0), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
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