Use the new helper to make the code more readable.
Change-Id: I11b2a79dbc6f93f6cfde382bcc00dd7ff710d908
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6375
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
#endif
#include "imp.h"
+#include <helper/align.h>
#include <helper/binarybuffer.h>
#include <target/algorithm.h>
#include <target/armv7m.h>
* max_flash_size is always power of two, so max_pages too
*/
uint32_t max_pages = stm32l4_info->part_info->max_flash_size_kb / page_size_kb;
- assert((max_pages & (max_pages - 1)) == 0);
+ assert(IS_PWR_OF_2(max_pages));
/* in dual bank mode number of pages is doubled, but extra bit is bank selection */
stm32l4_info->wrpxxr_mask = ((max_pages >> (stm32l4_info->dual_bank_mode ? 1 : 0)) - 1);
#endif
#include "imp.h"
+#include <helper/align.h>
#include <helper/binarybuffer.h>
#include <target/algorithm.h>
#include <target/armv7m.h>
LOG_DEBUG("Infineon XMC1000 write at 0x%08" PRIx32 " (%" PRIu32 " bytes)",
offset, byte_count);
- if (offset & (NVM_BLOCK_SIZE - 1)) {
+ if (!IS_ALIGNED(offset, NVM_BLOCK_SIZE)) {
LOG_ERROR("offset 0x%" PRIx32 " breaks required block alignment",
offset);
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
}
- if (byte_count & (NVM_BLOCK_SIZE - 1)) {
+ if (!IS_ALIGNED(byte_count, NVM_BLOCK_SIZE)) {
LOG_WARNING("length %" PRIu32 " is not block aligned, rounding up",
byte_count);
}
#include "config.h"
#endif
+#include <helper/align.h>
#include <helper/time_support.h>
#include "mips32.h"
goto exit; /* Nothing to do */
/* make sure clsiz is power of 2 */
- if (clsiz & (clsiz - 1)) {
+ if (!IS_PWR_OF_2(clsiz)) {
LOG_DEBUG("clsiz must be power of 2");
ctx.retval = ERROR_FAIL;
goto exit;
#include "config.h"
#endif
+#include <helper/align.h>
#include <helper/time_support.h>
#include <jtag/jtag.h>
#include <flash/nor/core.h>
uint32_t rp = fifo_start_addr;
/* validate block_size is 2^n */
- assert(!block_size || !(block_size & (block_size - 1)));
+ assert(IS_PWR_OF_2(block_size));
retval = target_write_u32(target, wp_addr, wp);
if (retval != ERROR_OK)
break;
}
- if (((rp - fifo_start_addr) & (block_size - 1)) || rp < fifo_start_addr || rp >= fifo_end_addr) {
+ if (!IS_ALIGNED(rp - fifo_start_addr, block_size) || rp < fifo_start_addr || rp >= fifo_end_addr) {
LOG_ERROR("corrupted fifo read pointer 0x%" PRIx32, rp);
break;
}
uint32_t rp = fifo_start_addr;
/* validate block_size is 2^n */
- assert(!block_size || !(block_size & (block_size - 1)));
+ assert(IS_PWR_OF_2(block_size));
retval = target_write_u32(target, wp_addr, wp);
if (retval != ERROR_OK)
break;
}
- if (((wp - fifo_start_addr) & (block_size - 1)) || wp < fifo_start_addr || wp >= fifo_end_addr) {
+ if (!IS_ALIGNED(wp - fifo_start_addr, block_size) || wp < fifo_start_addr || wp >= fifo_end_addr) {
LOG_ERROR("corrupted fifo write pointer 0x%" PRIx32, wp);
break;
}