target/hla_target: try to re-examine under reset in hl_assert_reset()

An application often idling in real sleep mode may make a Cortex-M target
hard to access as CPU clock are gated and debug requests are responded
by WAIT ack.

Try to examine the target under reset as the last resort.

Change-Id: I7c3de39fb1e6c23b76e2a0a85ab75f23aac94c4d
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7229
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

diff --git a/src/target/hla_target.c b/src/target/hla_target.c
index 33126d65a8c82e6b3a663f469ea4b01188c63f6c..8c35a90cb2a46c93cd17daed2f5f12f071cb0eac 100644 (file)
--- a/src/target/hla_target.c
+++ b/src/target/hla_target.c
@@ -347,6 +347,13 @@ static int hl_assert_reset(struct target *target)
 
        adapter->layout->api->write_debug_reg(adapter->handle, DCB_DHCSR, DBGKEY|C_DEBUGEN);
 
+       if (!target_was_examined(target) && !target->defer_examine
+               && srst_asserted && res == ERROR_OK) {
+               /* If the target is not examined, now under reset it is good time to retry examination */
+               LOG_TARGET_DEBUG(target, "Trying to re-examine under reset");
+               target_examine_one(target);
+       }
+
        /* only set vector catch if halt is requested */
        if (target->reset_halt)
                adapter->layout->api->write_debug_reg(adapter->handle, DCB_DEMCR, TRCENA|VC_CORERESET);