Code Review / openocd.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | review | tree
raw | patch | inline | side by side (parent: 4ba8388)
aarch64: formalize use of CTI in halt and resume 47/3747/5
authorMatthias Welwarsky <matthias.welwarsky@sysgo.com>
Fri, 16 Sep 2016 09:02:36 +0000 (11:02 +0200)
committerMatthias Welwarsky <matthias.welwarsky@sysgo.com>
Fri, 10 Feb 2017 13:01:38 +0000 (14:01 +0100)
Use configured CTI base address instead of hardcoded value, if
available.
Use symbolic constants instead of raw hex offsets.
Trim halt and resume code to what is actually necessary.

Change-Id: I4997c2bcca7cebf5ad78859a6a12abe8639594ed
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
src/target/aarch64.c patch | blob | history
src/target/armv8.h patch | blob | history

diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index d06e6684dcba7eca97ef1cfd217416b526c80fc4..4097d116066ee6d8a27b570e993f9a9e75b33f14 100644 (file)
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -796,59 +796,49 @@ static int aarch64_halt(struct target *target)
        uint32_t dscr;
        struct armv8_common *armv8 = target_to_armv8(target);
 
-       retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + 0x10000 + 0, &dscr);
+       /* enable CTI*/
        retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + 0x10000 + 0, 1);
-       retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + 0x10000 + 0, &dscr);
+                       armv8->cti_base + CTI_CTR, 1);
+       if (retval != ERROR_OK)
+               return retval;
 
-       retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + 0x10000 + 0x140, &dscr);
        retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + 0x10000 + 0x140, 6);
-       retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + 0x10000 + 0x140, &dscr);
+                       armv8->cti_base + CTI_GATE, 3);
+       if (retval != ERROR_OK)
+               return retval;
 
-       retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + 0x10000 + 0xa0, &dscr);
        retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + 0x10000 + 0xa0, 5);
-       retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + 0x10000 + 0xa0, &dscr);
-
-       retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + 0x10000 + 0xa4, &dscr);
-       retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + 0x10000 + 0xa4, 2);
-       retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + 0x10000 + 0xa4, &dscr);
+                       armv8->cti_base + CTI_OUTEN0, 1);
+       if (retval != ERROR_OK)
+               return retval;
 
-       retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + 0x10000 + 0x20, &dscr);
        retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + 0x10000 + 0x20, 4);
-       retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + 0x10000 + 0x20, &dscr);
+                       armv8->cti_base + CTI_OUTEN1, 2);
+       if (retval != ERROR_OK)
+               return retval;
 
        /*
-        * enter halting debug mode
+        * add HDE in halting debug mode
         */
        retval = mem_ap_read_atomic_u32(armv8->debug_ap,
                        armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
        if (retval != ERROR_OK)
                return retval;
 
-#      /* STATUS */
-       retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + 0x10000 + 0x134, &dscr);
+       retval = mem_ap_write_atomic_u32(armv8->debug_ap,
+                       armv8->debug_base + CPUV8_DBG_DSCR, dscr | DSCR_HDE);
+       if (retval != ERROR_OK)
+               return retval;
 
-       retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + 0x10000 + 0x1c, &dscr);
        retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + 0x10000 + 0x1c, 1);
-       retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + 0x10000 + 0x1c, &dscr);
+                       armv8->cti_base + CTI_APPPULSE, 1);
+       if (retval != ERROR_OK)
+               return retval;
+
+       retval = mem_ap_write_atomic_u32(armv8->debug_ap,
+                       armv8->cti_base + CTI_INACK, 1);
+       if (retval != ERROR_OK)
+               return retval;
 
 
        long long then = timeval_ms();
@@ -857,7 +847,7 @@ static int aarch64_halt(struct target *target)
                                armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
                if (retval != ERROR_OK)
                        return retval;
-               if ((dscr & DSCR_CORE_HALTED) != 0)
+               if ((dscr & DSCRV8_HALT_MASK) != 0)
                        break;
                if (timeval_ms() > then + 1000) {
                        LOG_ERROR("Timeout waiting for halt");
@@ -969,23 +959,7 @@ static int aarch64_internal_restart(struct target *target)
                LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
 
        retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + CPUV8_DBG_DSCR, dscr & ~DSCR_ITR_EN);
-       if (retval != ERROR_OK)
-               return retval;
-
-       retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + CPUV8_DBG_DRCR, DRCR_RESTART |
-                       DRCR_CLEAR_EXCEPTIONS);
-       if (retval != ERROR_OK)
-               return retval;
-
-       retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + 0x10000 + 0x10, 1);
-       if (retval != ERROR_OK)
-               return retval;
-
-       retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + 0x10000 + 0x1c, 2);
+                       armv8->cti_base + CTI_APPPULSE, 2);
        if (retval != ERROR_OK)
                return retval;
 
@@ -995,7 +969,7 @@ static int aarch64_internal_restart(struct target *target)
                                armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
                if (retval != ERROR_OK)
                        return retval;
-               if ((dscr & DSCR_CORE_RESTARTED) != 0)
+               if ((dscr & DSCR_HDE) != 0)
                        break;
                if (timeval_ms() > then + 1000) {
                        LOG_ERROR("Timeout waiting for resume");
@@ -1061,11 +1035,11 @@ static int aarch64_resume(struct target *target, int current,
        if (!debug_execution) {
                target->state = TARGET_RUNNING;
                target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
-               LOG_DEBUG("target resumed at 0x%" PRIu64, addr);
+               LOG_DEBUG("target resumed at 0x%" PRIx64, addr);
        } else {
                target->state = TARGET_DEBUG_RUNNING;
                target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
-               LOG_DEBUG("target debug resumed at 0x%" PRIu64, addr);
+               LOG_DEBUG("target debug resumed at 0x%" PRIx64, addr);
        }
 
        return ERROR_OK;
@@ -2316,6 +2290,12 @@ static int aarch64_examine_first(struct target *target)
        } else
                armv8->debug_base = target->dbgbase;
 
+       LOG_DEBUG("Target ctibase is 0x%x", target->ctibase);
+       if (target->ctibase == 0)
+               armv8->cti_base = target->ctibase = armv8->debug_base + 0x1000;
+       else
+               armv8->cti_base = target->ctibase;
+
        retval = mem_ap_write_atomic_u32(armv8->debug_ap,
                        armv8->debug_base + CPUV8_DBG_LOCKACCESS, 0xC5ACCE55);
        if (retval != ERROR_OK) {
diff --git a/src/target/armv8.h b/src/target/armv8.h
index 41edb991418b719319de398c13e2dd658b1fdb20..9c6ccce470213483c1dfc289bc826bb9f02e965e 100644 (file)
--- a/src/target/armv8.h
+++ b/src/target/armv8.h
@@ -130,6 +130,8 @@ struct armv8_common {
        /* Core Debug Unit */
        struct arm_dpm dpm;
        uint32_t debug_base;
+       uint32_t cti_base;
+
        struct adiv5_ap *debug_ap;
        struct adiv5_ap *memory_ap;
        bool memory_ap_available;
@@ -191,6 +193,35 @@ target_to_armv8(struct target *target)
 
 #define CPUV8_DBG_AUTHSTATUS   0xFB8
 
+/*define CTI(cross trigger interface)*/
+#define CTI_CTR                                0x0
+#define CTI_INACK                      0x10
+#define CTI_APPSET                     0x14
+#define CTI_APPCLEAR           0x18
+#define CTI_APPPULSE           0x1C
+#define CTI_INEN0                      0x20
+#define CTI_INEN1                      0x24
+#define CTI_INEN2                      0x28
+#define CTI_INEN3                      0x2C
+#define CTI_INEN4                      0x30
+#define CTI_INEN5                      0x34
+#define CTI_INEN6                      0x38
+#define CTI_INEN7                      0x3C
+#define CTI_OUTEN0                     0xA0
+#define CTI_OUTEN1                     0xA4
+#define CTI_OUTEN2                     0xA8
+#define CTI_OUTEN3                     0xAC
+#define CTI_OUTEN4                     0xB0
+#define CTI_OUTEN5                     0xB4
+#define CTI_OUTEN6                     0xB8
+#define CTI_OUTEN7                     0xBC
+#define CTI_TRIN_STATUS                0x130
+#define CTI_TROUT_STATUS       0x134
+#define CTI_CHIN_STATUS                0x138
+#define CTI_CHOU_STATUS                0x13C
+#define CTI_GATE                       0x140
+#define CTI_UNLOCK                     0xFB0
+
 
 int armv8_arch_state(struct target *target);
 int armv8_identify_cache(struct target *target);
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)