#include "rtos.h"
#include "target/armv7m.h"
+#include "rtos_chibios_stackings.h"
static const struct stack_register_offset rtos_chibios_arm_v7m_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
{ ARMV7M_R0, -1, 32 }, /* r0 */
#ifndef OPENOCD_RTOS_RTOS_CHIBIOS_STACKINGS_H
#define OPENOCD_RTOS_RTOS_CHIBIOS_STACKINGS_H
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
#include "rtos.h"
extern const struct rtos_register_stacking rtos_chibios_arm_v7m_stacking;
#endif
#include "rtos.h"
-#include "rtos_standard_stackings.h"
#include "target/armv7m.h"
+#include "rtos_standard_stackings.h"
+#include "rtos_ecos_stackings.h"
/* For Cortex-M eCos applications the actual thread context register layout can
* be different between active threads of an application depending on whether
#ifndef OPENOCD_RTOS_RTOS_ECOS_STACKINGS_H
#define OPENOCD_RTOS_RTOS_ECOS_STACKINGS_H
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
#include "rtos.h"
extern const struct rtos_register_stacking rtos_ecos_cortex_m3_stacking;
#include "rtos.h"
#include "target/armv7m.h"
#include "rtos_standard_stackings.h"
+#include "rtos_embkernel_stackings.h"
static const struct stack_register_offset rtos_embkernel_cortex_m_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
{ ARMV7M_R0, 0x24, 32 }, /* r0 */
#ifndef OPENOCD_RTOS_RTOS_EMBKERNEL_STACKINGS_H
#define OPENOCD_RTOS_RTOS_EMBKERNEL_STACKINGS_H
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
#include "rtos.h"
extern const struct rtos_register_stacking rtos_embkernel_cortex_m_stacking;
#include "rtos.h"
#include "target/armv7m.h"
-
+#include "rtos_mqx_stackings.h"
/*
* standard exception stack
#ifndef OPENOCD_RTOS_RTOS_MQX_STACKINGS_H
#define OPENOCD_RTOS_RTOS_MQX_STACKINGS_H
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
#include "rtos.h"
extern const struct rtos_register_stacking rtos_mqx_arm_v7m_stacking;
#include "rtos.h"
#include "target/armv7m.h"
#include "rtos_standard_stackings.h"
+#include "rtos_riot_stackings.h"
/* This works for the M0 and M34 stackings as xPSR is in a fixed
* location
#ifndef OPENOCD_RTOS_RTOS_RIOT_STACKINGS_H
#define OPENOCD_RTOS_RTOS_RIOT_STACKINGS_H
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
#include "rtos.h"
extern const struct rtos_register_stacking rtos_riot_cortex_m0_stacking;
extern const struct rtos_register_stacking rtos_riot_cortex_m34_stacking;
#endif /* OPENOCD_RTOS_RTOS_RIOT_STACKINGS_H */
-
#include "rtos.h"
#include "target/armv7m.h"
+#include "rtos_standard_stackings.h"
static const struct stack_register_offset rtos_standard_cortex_m3_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
{ ARMV7M_R0, 0x20, 32 }, /* r0 */
#ifndef OPENOCD_RTOS_RTOS_STANDARD_STACKINGS_H
#define OPENOCD_RTOS_RTOS_STANDARD_STACKINGS_H
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
#include "rtos.h"
extern const struct rtos_register_stacking rtos_standard_cortex_m3_stacking;
#include "config.h"
#endif
-#include <helper/types.h>
-#include <rtos/rtos.h>
-#include <rtos/rtos_standard_stackings.h>
-#include <target/armv7m.h>
-#include <target/esirisc.h>
+#include "rtos.h"
+#include "target/armv7m.h"
+#include "target/esirisc.h"
+#include "rtos_standard_stackings.h"
+#include "rtos_ucos_iii_stackings.h"
static const struct stack_register_offset rtos_ucos_iii_cortex_m_stack_offsets[] = {
{ ARMV7M_R0, 0x20, 32 }, /* r0 */
#ifndef OPENOCD_RTOS_RTOS_UCOS_III_STACKINGS_H
#define OPENOCD_RTOS_RTOS_UCOS_III_STACKINGS_H
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <rtos/rtos.h>
+#include "rtos.h"
extern const struct rtos_register_stacking rtos_ucos_iii_cortex_m_stacking;
extern const struct rtos_register_stacking rtos_ucos_iii_esi_risc_stacking;